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(2)

• CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications.
  G. G. Shahidi and James D. Warnock and James Comfort and Stephen E. Fischer and Patricia A. McFarland and Alexandre Acovic and Terry I. Chappell and Barbara A. Chappell and Tak H. Ning and Carl J. Anderson and Robert H. Dennard and J. Y.-C. Sun and Michael R. Polcari and Bijan Davari IBM Journal of Research and Development 39 229-244 (1995)
  to dblp by dblp on 2008-08-20 00:00:00
  | URL | BibTeX  
• Use of scanning capacitance microscopy for controlling wafer processing.
  O. Jeandupeux and V. Marsico and A. Acovic and P. Fazan and H. Brune and K. Kern Microelectronics Reliability 42 225-231 (2002)
  to dblp by dblp on 2007-03-25 00:00:00
  | URL | BibTeX