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Preamble design, system acquisition, and determination in modern OFDMA cellular communications: an overview.
Michael Mao Wang, Avneesh Agrawal, Aamod Khandekar, and Sandeep R. Aedudodla IEEE Communications Magazine 49(7):164-175 (2011)
to dblp by dblp on Feb 13, 2012, 12:00 AM
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Image Enhancement Algorithm for Ink-on-Paper Fingerprints.
Raghav Agrawal, Badrinath G. Srinivas, and Phalguni Gupta ICIC 1, volume 6838 of Lecture Notes in Computer Science, page 311-318. Springer, (2011)
to dblp by dblp on Feb 10, 2012, 12:00 AM
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An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited.
Dharam Vir Das, Sharad C. Seth, Paul T. Wagner, John C. Anderson, and Vishwani D. Agrawal ITC, page 712-720. IEEE Computer Society, (1990)
to dblp by dblp on Feb 9, 2012, 12:00 AM
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CMP3F: a high speed fault simulator for the Connection Machine.
Ajit Agrawal, and Debashis Bhattacharya ITC, page 410-416. IEEE Computer Society, (1990)
to dblp by dblp on Feb 9, 2012, 12:00 AM
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Emulating goliath storage systems with David.
Nitin Agrawal, Leo Arulraj, Andrea C. Arpaci-Dusseau, and Remzi H. Arpaci-Dusseau TOS 7(4):12 (2012)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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Fault Simulation in a Pipelined Multiprocessor System.
Prathima Agrawal, Vishwani D. Agrawal, Kwang-Ting Cheng, and R. Tutundjian ITC, page 727-734. IEEE Computer Society, (1989)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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A non-enumerative path delay fault simulator for sequential circuits.
Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, and Shianling Wu ITC, page 934-943. IEEE Computer Society, (1998)
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Effective Path Selection for Delay Fault Testing of Sequential Circuits.
Tapan J. Chakraborty, and Vishwani D. Agrawal ITC, page 998-1003. IEEE Computer Society, (1997)
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Algorithms for Switch Level Delay Fault Simulation.
Soumitra Bose, Vishwani D. Agrawal, and Thomas G. Szymanski ITC, page 982-991. IEEE Computer Society, (1997)
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An Exact Non-Enumerative Fault Simulator for Path-Delay Faults.
Marwan A. Gharaybeh, Michael L. Bushnell, and Vishwani D. Agrawal ITC, page 276-285. IEEE Computer Society, (1996)
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Synthesis of Self-Testing Finite State Machines from High-Level Specifications.
Vishwani D. Agrawal, Ronald D. Blanton, and Maurizio Damiani ITC, page 757-766. IEEE Computer Society, (1996)
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Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests.
Marwan A. Gharaybeh, Michael L. Bushnell, and Vishwani D. Agrawal ITC, page 139-148. IEEE Computer Society, (1995)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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High-Performance Circuit Testing with Slow-Speed Testers.
Vishwani D. Agrawal, and Tapan J. Chakraborty ITC, page 302-310. IEEE Computer Society, (1995)
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Generation of Compact Delay Tests by Multiple-Path Activation.
Soumitra Bose, Prathima Agrawal, and Vishwani D. Agrawal ITC, page 714-723. IEEE Computer Society, (1993)
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A Synthesis Approach to Design for Testability.
Suman Kanjilal, Srimat T. Chakradhar, and Vishwani D. Agrawal ITC, page 754-763. IEEE Computer Society, (1993)
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Estimating the Quality of Manufactured Digital Sequential Circuits.
Dharam Vir Das, Sharad C. Seth, and Vishwani D. Agrawal ITC, page 210-217. IEEE Computer Society, (1991)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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Register-transfer level fault modeling and test evaluation techniques for VLSI circuits.
Pradip A. Thaker, Vishwani D. Agrawal, and Mona E. Zaghloul ITC, page 940-949. IEEE Computer Society, (2000)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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Measuring code edges of ADCs using interpolation and its application to offset and gain error testing.
Pramodchandran N. Variyam, and Vinay Agrawal ITC, page 349-357. IEEE Computer Society, (2000)
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Combinational test generation for various classes of acyclic sequential circuits.
Yong Chang Kim, Vishwani D. Agrawal, and Kewal K. Saluja ITC, page 1078-1087. IEEE Computer Society, (2001)
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Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply.
Kyungseok Kim, and Vishwani D. Agrawal J. Low Power Electronics 7(4):460-470 (2011)
to dblp by dblp on Feb 7, 2012, 12:00 AM
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