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A Virtual Hardware System on a Dynamically Reconfigurable Logic Device.
Yuichiro Shibata, Masaki Uno, Hideharu Amano, Koichiro Furuta, Taro Fujii, and Masato Motomura FCCM, page 295-296. IEEE Computer Society, (2000)
to dblp by dblp on Feb 9, 2012, 12:00 AM
URL | BibTeX
An implementation of out-of-order execution system for acceleration of computational fluid dynamics on FPGAs.
Takayuki Akamine, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, and Hideharu Amano SIGARCH Computer Architecture News 39(4):50-55 (2011)
to dblp by dblp on Feb 8, 2012, 12:00 AM
URL | BibTeX
High speed CRC with 64-bit generator polynomial on an FPGA.
Amila Akagic, and Hideharu Amano SIGARCH Computer Architecture News 39(4):72-77 (2011)
to dblp by dblp on Feb 8, 2012, 12:00 AM
URL | BibTeX
Foreword.
Hideharu Amano IEICE Transactions 95-D(2):293 (2012)
to dblp by dblp on Feb 7, 2012, 12:00 AM
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Statistical Estimation for CAPM with Long-Memory Dependence.
Tomoyuki Amano, Tsuyoshi Kato, and Masanobu Taniguchi ADS (2012)
to dblp by dblp on Feb 2, 2012, 12:00 AM
URL | BibTeX
Optimal Portfolios with End-of-Period Target.
Hiroshi Shiraishi, Hiroaki Ogata, Tomoyuki Amano, Valentin Patilea, David Veredas, and Masanobu Taniguchi ADS (2012)
to dblp by dblp on Feb 2, 2012, 12:00 AM
URL | BibTeX
How to Solve the Torus Puzzle.
Kazuyuki Amano, Yuta Kojima, Toshiya Kurabayashi, Keita Kurihara, Masahiro Nakamura, Ayaka Omi, Toshiyuki Tanaka, and Koichi Yamazaki Algorithms 5(1):18-29 (2012)
to dblp by dblp on Jan 31, 2012, 12:00 AM
URL | BibTeX
Cool Mega-Array: A highly energy efficient reconfigurable accelerator.
Nobuaki Ozaki, Y. Yoshihiro, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, and Masaaki Kondo FPT, page 1-8. IEEE, (2011)
to dblp by dblp on Jan 27, 2012, 12:00 AM
URL | BibTeX
The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator.
Kazuei Hironaka, Nobuaki Ozaki, and Hideharu Amano FPT, page 1-4. IEEE, (2011)
to dblp by dblp on Jan 25, 2012, 12:00 AM
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Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations.
Masayuki Kimura, Kazuei Hironaka, and Hideharu Amano FPT, page 1-8. IEEE, (2011)
to dblp by dblp on Jan 25, 2012, 12:00 AM
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On Directional vs. General Randomized Decision Tree Complexity for Read-Once Formulas.
Kazuyuki Amano Chicago J. Theor. Comput. Sci. (2011)
to dblp by dblp on Jan 23, 2012, 12:00 AM
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Non-negative matrix factorization considering given vectors in a basis.
Yuta Amano, Akira Tanaka, and Masaaki Miyakoshi GrC, page 48-53. IEEE, (2011)
to dblp by dblp on Jan 20, 2012, 12:00 AM
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Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth.
Kazuei Hironaka, and Hideharu Amano ReConFig, page 404-409. IEEE Computer Society, (2011)
to dblp by dblp on Jan 20, 2012, 12:00 AM
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Proposal of Auto MPI Expansion Tool for Cell Broadband Engine Cluster.
Tetsuya Nakahama, Masahiro Yamada, Masato Yoshimi, and Hideharu Amano ICNC, page 166-172. IEEE Computer Society, (2011)
to dblp by dblp on Jan 17, 2012, 12:00 AM
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Vegeta: An Implementation and Evaluation of Development-Support Middleware on Multiple OpenCL Platform.
Akihiro Shitara, Tetsuya Nakahama, Masahiro Yamada, Toshiaki Kamata, Yuri Nishikawa, Masato Yoshimi, and Hideharu Amano ICNC, page 141-147. IEEE Computer Society, (2011)
to dblp by dblp on Jan 17, 2012, 12:00 AM
URL | BibTeX
Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects.
Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, and Hideharu Amano ICNC, page 50-57. IEEE Computer Society, (2011)
to dblp by dblp on Jan 17, 2012, 12:00 AM
URL | BibTeX
Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot.
Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, and Hironori Nakajo PDPTA, page 787-793. CSREA Press, (2007)
to dblp by dblp on Jan 17, 2012, 12:00 AM
URL | BibTeX
Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor.
Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, and Hideharu Amano IEICE Transactions 94-A(12):2619-2627 (2011)
to dblp by dblp on Jan 13, 2012, 12:00 AM
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Association-Based Natural Language Processing with Neural Networks.
Kazuhiro Kimura, Takashi Suzuoka, and Shin'ya Amano ACL, page 224-231. ACL, (1992)
to dblp by dblp on Dec 23, 2011, 12:00 AM
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Experiences with an On-Line Translating Dialogue System.
Seiji Miike, Koichi Hasebe, Harold L. Somers, and Shin'ya Amano ACL, page 155-162. ACL, (1988)
to dblp by dblp on Dec 23, 2011, 12:00 AM
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