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Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.
Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, and Mateo Valero PACT, page 361-371. IEEE Computer Society, (2011)
to dblp by dblp on Jan 5, 2012, 12:00 AM
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Circuit design of a dual-versioning L1 data cache for optimistic concurrency.
Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, and Mateo Valero ACM Great Lakes Symposium on VLSI, page 325-330. ACM, (2011)
to dblp by dblp on May 11, 2011, 12:00 AM
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EazyHTM: eager-lazy hardware transactional memory.
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris, and Mateo Valero MICRO, page 145-155. ACM, (2009)
to dblp by dblp on Jul 21, 2010, 4:01 PM
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