BibSonomy ::  author ::

bookmarks

publications

(11)

• Undetected disk errors in RAID arrays.
  James L. Hafner and Veera Deenadhayalan and Wendy Belluomini and Krishnakumar Rao IBM Journal of Research and Development 52 413-426 (2008)
  to dblp by dblp on 2008-08-20 00:00:00
  | URL | BibTeX  
• Flipstone: managing storage with fail-in-place and deferred maintenance service models.
  Mohammad Banikazemi and Jim Hafner and Wendy Belluomini and KK Rao and Dan E. Poff and Bülent Abali Operating Systems Review 42 54-62 (2008)
  to dblp by dblp on 2008-05-08 00:00:00
  | URL | BibTeX  
• A low latency and low power dynamic Carry Save Adder.
  Ramyanshu Datta and Jacob A. Abraham and Robert K. Montoye and Wendy Belluomini and Hung Ngo and Chandler McDowell and Jente B. Kuang and Kevin J. Nowka ISCAS (2) 477-480 (2004)
  to dblp by dblp on 2007-05-03 00:00:00
  | URL | BibTeX  
• Limited switch dynamic logic circuits for high-speed low-power circuit design.
  Wendy Belluomini and Damir Jamsek and Andrew K. Martin and Chandler McDowell and Robert K. Montoye and Hung C. Ngo and Jun Sawada IBM Journal of Research and Development 50 277-286 (2006)
  to dblp by dblp on 2006-08-31 00:00:00
  | URL | BibTeX  
• Timed Circuit Synthesis Using Implicit Methods.
  Robert Thacker and Wendy Belluomini and Chris J. Myers VLSI Design 181-188 (1999)
  to dblp by dblp on 2006-05-18 00:00:00
  | URL | BibTeX  
• Timed circuit verification using TEL structures.
  Wendy Belluomini and Chris J. Myers and H. Peter Hofstee IEEE Trans. on CAD of Integrated Circuits and Systems 20 129-146 (2001)
  to dblp by dblp on 2006-05-11 00:00:00
  | URL | BibTeX  
• Timed state space exploration using POSETs.
  Wendy Belluomini and Chris J. Myers IEEE Trans. on CAD of Integrated Circuits and Systems 19 501-520 (2000)
  to dblp by dblp on 2006-05-11 00:00:00
  | URL | BibTeX  
• Timed circuits: a new paradigm for high-speed design.
  Chris J. Myers and Wendy Belluomini and Kip Kallpack and Eric Peskin and Hao Zheng ASP-DAC 335-340 (2001)
  to dblp by dblp on 2006-02-10 00:00:00
  | URL | BibTeX  
• Verification of Delayed-Reset Domino Circuits Using ATACS.
  Wendy Belluomini and Chris J. Myers and H. Peter Hofstee ASYNC 3-12 (1999)
  to dblp by dblp on 2004-07-05 00:00:00
  | URL | BibTeX  
• Efficient Timing Analysis Algorithms for Timed State Space Exploration.
  Wendy Belluomini and Chris J. Myers ASYNC 88-100 (1997)
  to dblp by dblp on 2004-07-05 00:00:00
  | URL | BibTeX  
• Verification of Timed Systems Using POSETs.
  Wendy Belluomini and Chris J. Myers CAV 403-415 (1998)
  to dblp by dblp on 2002-02-28 00:00:00
  | URL | BibTeX