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Power and thermal characterization of POWER6 system.
Victor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, and Pradip Bose PACT, page 7-18. ACM, (2010)
to dblp by dblp on Feb 14, 2011, 12:00 AM
URL | BibTeX
Software-Controlled Priority Characterization of POWER5 Processor.
Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, and Mateo Valero ISCA, page 415-426. IEEE, (2008)
to dblp by dblp on Mar 20, 2009, 12:00 AM
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A dynamic scheduler for balancing HPC applications.
Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, and Mateo Valero SC, page 41. IEEE/ACM, (2008)
to dblp by dblp on Nov 17, 2008, 12:00 AM
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Balancing HPC applications through smart allocation of resources in MT processors.
Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Julita Corbalan, Jesús Labarta, and Mateo Valero IPDPS, page 1-12. IEEE, (2008)
to dblp by dblp on Oct 31, 2008, 12:00 AM
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Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation.
Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, and Mateo Valero ARCS, volume 4934 of Lecture Notes in Computer Science, page 173-187. Springer, (2008)
to dblp by dblp on Feb 28, 2008, 12:00 AM
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