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publications

(8)

• Photonics in switching: Architectures, systems and enabling technologies.
  Carla Raffaelli and Kyriakos Vlachos and Nicola Andriolli and Dimitrios Apostolopoulos and Jakob Buron and Ruth van Caenegem and Grzegorz Danilewicz and Jorge M. Finochietto and Joan García-Haro and Dimitrios Klonidis and Mike O'Mahony and Guido Maier and Achille Pattavina and Pablo Pavon-Marino and Sarah Ruepp and Michele Savi and Mirco Scaffardi and Ioannis Tomkos and Anna Tzanakaki and Lena Wosinska Computer Networks 52 1873-1890 (2008)
  to dblp by dblp on 2008-08-13 00:00:00
  | URL | BibTeX  
• Restoration in all-optical GMPLS networks with limited wavelength conversion.
  Sarah Ruepp and Nicola Andriolli and Jakob Buron and Lars Dittmann and Lars Ellegard Computer Networks 52 1951-1964 (2008)
  to dblp by dblp on 2008-06-12 00:00:00
  | URL | BibTeX  
• Parallel-pipeline 8×8 forward 2-D ICT processor chip for image coding.
  Gustavo A. Ruiz and Juan A. Michell and Angel M. Buron IEEE Transactions on Signal Processing 53 714-723 (2005)
  to dblp by dblp on 2008-02-27 00:00:00
  | URL | BibTeX  
• Haar wavelet based processor scheme for image coding with low circuit complexity.
  F. Javier Díaz and Angel M. Buron and José M. Solana Computers & Electrical Engineering 33 109-126 (2007)
  to dblp by dblp on 2007-10-01 00:00:00
  | URL | BibTeX  
• High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip.
  Gustavo A. Ruiz and Juan A. Michell and Angel M. Buron VLSI Signal Processing 45 161-175 (2006)
  to dblp by dblp on 2007-09-11 00:00:00
  | URL | BibTeX  
• Segmentation-Based Path Switching Mechanism for Reduced Data Losses in OBS Networks.
  Anna V. Manolova and Jakob Buron and Sarah Ruepp and Lars Dittmann and Lars Ellegard ONDM 338-347 (2007)
  to dblp by dblp on 2007-07-25 00:00:00
  | URL | BibTeX  
• High throughput 2D DCT/IDCT processor for video coding.
  Gustavo A. Ruiz and Juan A. Michell and Angel M. Buron ICIP (3) 1036-1039 (2005)
  to dblp by dblp on 2007-05-04 00:00:00
  | URL | BibTeX  
• Parallel-pipelined architecture for 2-D ICT VLSI implementation.
  Juan A. Michell and Gustavo A. Ruiz and Angel M. Buron ICIP (3) 89-92 (2003)
  to dblp by dblp on 2005-07-14 00:00:00
  | URL | BibTeX