BibSonomy :: author  ::

bookmarks

publications

(34)

• Larrabee: A Many-Core x86 Architecture for Visual Computing
  Larry Seiler and Doug Carmean and Eric Sprangle and Tom Forsyth and Michael Abrash and Pradeep Dubey and Stephen Junkins and Adam Lake and Jeremy Sugerman and Robert Cavin and Roger Espasa and Ed Grochowski and Toni Juan and Pat Hanrahan ACM Trans. Graph. 27 1--15 (2008)
  to Intel Larrabee ManyCore PhD Proposal by gron and 1 other person on 2008-08-16 18:03:21
  | URL | BibTeX  
• Clocking Optimization and Distribution in Digital Systems with Scheduled Skews.
  Hong-Yean Hsieh and Wentai Liu and Paul D. Franzon and Ralph K. Cavin III VLSI Signal Processing 16 131-147 (1997)
  to dblp by dblp on 2008-08-07 00:00:00
  | URL | BibTeX  
• Larrabee: a many-core x86 architecture for visual computing.
  Larry Seiler and Doug Carmean and Eric Sprangle and Tom Forsyth and Michael Abrash and Pradeep Dubey and Stephen Junkins and Adam Lake and Jeremy Sugerman and Robert Cavin and Roger Espasa and Ed Grochowski and Toni Juan and Pat Hanrahan ACM Trans. Graph. 27 (2008)
  to dblp by dblp and 1 other person on 2008-08-05 00:00:00
  | URL | BibTeX  
• Boolean Logic and Alternative Information-Processing Devices
  George Bourianoff and Joe E. Brewer and Ralph Cavin and James A. Hutchby and Victor Zhirnov Computer 41 38-46 (2008)
  to imported by roos on 2008-05-23 20:27:38
  | BibTeX  
• Emerging Research Architectures
  Ralph Cavin and James A. Hutchby and Victor Zhirnov and Joe E. Brewer and George Bourianoff Computer 41 33-37 (2008)
  to imported by roos on 2008-05-23 20:27:38
  | BibTeX  
• Emerging Nanoscale Memory and Logic Devices: A Critical Assessment
  James A. Hutchby and Ralph Cavin and Victor Zhirnov and Joe E. Brewer and George Bourianoff Computer 41 28-32 (2008)
  to imported by roos on 2008-05-23 20:27:38
  | BibTeX  
• An Assessment of Integrated Digital Cellular Automata Architectures
  Victor Zhirnov and Ralph Cavin and Greg Leeming and Kosmas Galatsis Computer 41 38-44 (2008)
  to imported by roos on 2008-05-23 20:26:48
  | BibTeX  
• Current-mode signaling in deep submicrometer global interconnects.
  Rizwan Bashirullah and Wentai Liu and Ralph K. Cavin III IEEE Trans. VLSI Syst. 11 406-417 (2003)
  to dblp by dblp on 2007-11-13 00:00:00
  | URL | BibTeX  
• Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions.
  Wentai Liu and Tong-Fei Yeh and William E. Batchelor and Ralph K. Cavin III ISCA 167-174 (1988)
  to dblp by dblp on 2007-01-11 00:00:00
  | URL | BibTeX  
• A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability.
  Rizwan Bashirullah and Wentai Liu and Ralph K. Cavin III and Dale Edwards IEEE Trans. VLSI Syst. 12 876-880 (2004)
  to dblp by dblp on 2007-01-11 00:00:00
  | URL | BibTeX