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publications

(87)

• A Self-stabilizing Link-Cluster Algorithm in Mobile Ad Hoc Networks.
  Doina Bein and Ajoy Kumar Datta and Chakradhar R. Jagganagari and Vincent Villain ISPAN 436-441 (2005)
  to dblp by dblp on 2008-05-19 00:00:00
  | URL | BibTeX  
• HERMES: A Software Architecture for Visibility and Control in Wireless Sensor Network Deployments.
  Nupur Kothari and Kiran Nagaraja and Vijay Raghunathan and Florin Sultan and Srimat Chakradhar IPSN 395-406 (2008)
  to dblp by dblp on 2008-05-07 00:00:00
  | URL | BibTeX  
• Bottleneck removal algorithm for dynamic compaction and test cycles reduction.
  Srimat T. Chakradhar and Anand Raghunathan EURO-DAC 98-104 (1995)
  to dblp by dblp on 2008-04-09 00:00:00
  | URL | BibTeX  
• A hybrid scheme for compacting test responses with unknown values.
  Mango Chia-Tso Chao and Kwang-Ting Cheng and Seongmoon Wang and Srimat T. Chakradhar and Wenlong Wei ICCAD 513-519 (2007)
  to dblp by dblp on 2007-12-31 00:00:00
  | URL | BibTeX  
• Unknown-tolerance analysis and test-quality control for test response compaction using space compactors.
  Mango Chia-Tso Chao and Kwang-Ting Cheng and Seongmoon Wang and Srimat T. Chakradhar and Wenlong Wei DAC 1083-1088 (2006)
  to dblp by dblp on 2007-12-27 00:00:00
  | URL | BibTeX  
• H.264 HDTV Decoder Using Application-Specific Networks-On-Chip.
  Jiang Xu and Wayne Wolf and Jörg Henkel and Srimat T. Chakradhar ICME 1508-1511 (2005)
  to dblp by dblp on 2007-12-04 00:00:00
  | URL | BibTeX  
• A methodology for design, modeling, and analysis of networks-on-chip.
  Jiang Xu and Wayne Wolf and Jörg Henkel and Srimat T. Chakradhar ISCAS (2) 1778-1781 (2005)
  to dblp by dblp on 2007-12-03 00:00:00
  | URL | BibTeX  
• Synthesis of initializable asynchronous circuits.
  Srimat T. Chakradhar and Savita Banerjee and Rabindra K. Roy and Dhiraj K. Pradhan IEEE Trans. VLSI Syst. 4 254-263 (1996)
  to dblp by dblp on 2007-11-12 00:00:00
  | URL | BibTeX  
• Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC.
  Divya Arora and Anand Raghunathan and Srivaths Ravi and Murugan Sankaradass and Niraj K. Jha and Srimat T. Chakradhar IEEE Trans. VLSI Syst. 15 699-710 (2007)
  to dblp by dblp on 2007-11-04 00:00:00
  | URL | BibTeX  
• Testable Path Delay Fault Cover for Sequential Circuits.
  Angela Krstic and Srimat T. Chakradhar and Kwang-Ting Cheng J. Inf. Sci. Eng. 16 673-686 (2000)
  to dblp by dblp on 2007-10-24 00:00:00
  | URL | BibTeX