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Power-scan chain: design for analog testability.
Amir Zjajo, Hendrik J. Bergveld, Rodger Schuttert, and José Pineda de Gyvez ITC, page 8. IEEE, (2005)
to dblp by dblp on Feb 7, 2012, 12:00 AM
URL | BibTeX
Functional vs. multi-VDD testing of RF circuits.
Estella Silva, José Pineda de Gyvez, and Guido Gronthoud ITC, page 9. IEEE, (2005)
to dblp by dblp on Feb 7, 2012, 12:00 AM
URL | BibTeX
Word line pulsing technique for stability fault detection in SRAM cells.
Andrei Pavlov, Mohamed Azimane, José Pineda de Gyvez, and Manoj Sachdev ITC, page 10. IEEE, (2005)
to dblp by dblp on Feb 7, 2012, 12:00 AM
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An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage.
Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, and Yajun Ha J. Solid-State Circuits 45(3):668-680 (2010)
to dblp by dblp on Jan 9, 2012, 12:00 AM
URL | BibTeX
Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits.
Maurice Meijer, and José Pineda de Gyvez IEEE Trans. VLSI Syst. 20(1):42-51 (2012)
to dblp by dblp on Dec 19, 2011, 12:00 AM
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Dynamic voltage scaling based on supply current tracking using fuzzy Logic controller.
Hamid Reza Pourshaghaghi, and José Pineda de Gyvez ICECS, page 779-782. IEEE, (2009)
to dblp by dblp on Dec 12, 2011, 12:00 AM
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An energy-aware multiplier based on a Configurable-Reuse of points design methodology.
Sebastian M. Londono, and José Pineda de Gyvez ICECS, page 89-92. IEEE, (2009)
to dblp by dblp on Dec 12, 2011, 12:00 AM
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Power-performance optimization using fuzzy control of simultaneous supply voltage and body biasing scaling.
Hamid Reza Pourshaghaghi, and José Pineda de Gyvez ICECS, page 281-284. IEEE, (2010)
to dblp by dblp on Nov 29, 2011, 12:00 AM
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Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage.
Bo Liu, Hamid Reza Pourshaghaghi, Sebastian M. Londono, and José Pineda de Gyvez DSD, page 135-139. IEEE, (2011)
to dblp by dblp on Nov 21, 2011, 12:00 AM
URL | BibTeX
Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs.
Amir Zjajo, Qin Tang, Michel Berkelaar, José Pineda de Gyvez, Alessandro Di Bucchianico, and Nick van der Meijs IEEE Trans. on Circuits and Systems 58-I(1):164-175 (2011)
to dblp by dblp on Oct 20, 2011, 12:00 AM
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An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply.
Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, and Yajun Ha ISSCC, page 146-147. IEEE, (2009)
to dblp by dblp on Oct 19, 2011, 12:00 AM
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Encoded-Low Swing Technique for Ultra Low Power Interconnect.
Rohini Krishnan, José Pineda de Gyvez, and Harry J. M. Veendrick FPL, volume 2778 of Lecture Notes in Computer Science, page 240-251. Springer, (2003)
to dblp by dblp on Jul 5, 2011, 12:00 AM
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Efficient testing and diagnosis of faulty power switches in SOCs.
Sandeep Kumar Goel, Maurice Meijer, and José Pineda de Gyvez IET Computers & Digital Techniques 1(3):230-236 (2007)
to dblp by dblp on Jun 22, 2011, 12:00 AM
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A forward body bias generator for digital CMOS circuits with supply voltage scaling.
Maurice Meijer, José Pineda de Gyvez, Ben Kup, Bert van Uden, Peter Bastiaansen, Marco Lammers, and Maarten Vertregt ISCAS, page 2482-2485. IEEE, (2010)
to dblp by dblp on Apr 14, 2011, 12:00 AM
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Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation.
Maurice Meijer, José Pineda de Gyvez, and Ajay Kapoor J. Low Power Electronics 6(4):521-532 (2010)
to dblp by dblp on Apr 12, 2011, 12:00 AM
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Analog Automatic Test Pattern Generation for Quasi-Static Structural Test.
Amir Zjajo, and José Pineda de Gyvez IEEE Trans. VLSI Syst. 17(10):1383-1391 (2009)
to dblp by dblp on Nov 16, 2010, 12:00 AM
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Body bias driven design synthesis for optimum performance per area.
Maurice Meijer, and José Pineda de Gyvez ISQED, page 472-477. IEEE, (2010)
to dblp by dblp on Jul 21, 2010, 4:00 PM
URL | BibTeX
Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm.
Amir Zjajo, Shaji Krishnan, and José Pineda de Gyvez DDECS, page 287-292. IEEE Computer Society, (2008)
to dblp by dblp on Sep 3, 2008, 12:00 AM
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Diagnostic Analysis of Static Errors in Multi-Step Analog to Digital Converters.
Amir Zjajo, and José Pineda de Gyvez DATE, page 74-79. IEEE, (2008)
to dblp by dblp on Aug 5, 2008, 12:00 AM
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Statistical noise margin estimation for sub-threshold combinational circuits.
Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, and Yajun Ha ASP-DAC, page 176-179. IEEE, (2008)
to dblp by dblp on May 6, 2008, 12:00 AM
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