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publications
(5)
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Technology, CAD tools, and designs for emerging 3D integration technology.
Syed M.
Alam
and Mike
Ignatowski
and Yuan
Xie
ACM Great Lakes Symposium on VLSI
1-2 (2008)
to
dblp
by
dblp
on 2008-05-13 00:00:00
|
URL
|
BibTeX
Interconnects in the Third Dimension: Design Challenges for 3D ICs.
Kerry
Bernstein
and Paul
Andry
and Jerome
Cann
and Philip G.
Emma
and David
Greenberg
and Wilfried
Haensch
and Mike
Ignatowski
and Steve
Koester
and John
Magerlein
and Ruchir
Puri
and Albert M.
Young
DAC
562-567 (2007)
to
dblp
by
dblp
on 2008-02-28 00:00:00
|
URL
|
BibTeX
A hierarchical gate array architecture and design methodology.
M.
Iachponi
and D.
Vail
and S.
Bierly
and A.
Ignatowski
DAC
439-442 (1985)
to
dblp
by
dblp
on 2007-01-22 00:00:00
|
URL
|
BibTeX
Exploitation of optical interconnects in future server architectures.
Alan F.
Benner
and Michael
Ignatowski
and Jeffrey A.
Kash
and Daniel M.
Kuchta
and Mark B.
Ritter
IBM Journal of Research and Development
49
755-776 (2005)
to
dblp
by
dblp
on 2006-09-05 00:00:00
|
URL
|
BibTeX
Analytical analysis of finite cache penalty and cycles per instruction of a multiprocessor memory hierarchy using miss rates and queuing theory.
Richard E.
Matick
and Thomas J.
Heller
and Michael
Ignatowski
IBM Journal of Research and Development
45
819-842 (2001)
to
dblp
by
dblp
on 2003-05-16 00:00:00
|
URL
|
BibTeX
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