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Cool Mega-Array: A highly energy efficient reconfigurable accelerator.
Nobuaki Ozaki, Y. Yoshihiro, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, and Masaaki Kondo FPT, page 1-8. IEEE, (2011)
to dblp by dblp on Jan 27, 2012, 12:00 AM
URL | BibTeX
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.
Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, and Masaaki Kondo IEEE Micro 31(6):6-18 (2011)
to dblp by dblp on Dec 20, 2011, 12:00 AM
URL | BibTeX
A Leakage Efficient Instruction TLB Design for Embedded Processors.
Zhao Lei, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, and Hideharu Amano IEICE Transactions 94-D(8):1565-1574 (2011)
to dblp by dblp on Oct 18, 2011, 12:00 AM
URL | BibTeX
Reducing instruction TLB's leakage power consumption for embedded processors.
Zhao Lei, Hui Xu, Daisuke Ikebuchi, Hideharu Amano, Tetsuya Sunata, and Mitaro Namiki Green Computing Conference, page 477-484. IEEE, (2010)
to dblp by dblp on Jul 5, 2011, 12:00 AM
URL | BibTeX
Geyser-2: The second prototype CPU with fine-grained run-time power gating.
Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, and Masaaki Kondo ASP-DAC, page 87-88. IEEE, (2011)
to dblp by dblp on May 15, 2011, 12:00 AM
URL | BibTeX
MoPH: a media performance system with a multi-touch interface.
Saburo Hirano, Takashi Ikebuchi, and Haruhiro Katayose Advances in Computer Entertainment Technology, page 20-23. ACM, (2010)
to dblp by dblp on May 5, 2011, 12:00 AM
URL | BibTeX
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs.
Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, and Hideharu Amano IEEE Trans. on CAD of Integrated Circuits and Systems 30(4):520-533 (2011)
to dblp by dblp on Apr 20, 2011, 12:00 AM
URL | BibTeX
A Leakage Efficient Data TLB Design for Embedded Processors.
Lei Zhao, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, and Hideharu Amano IEICE Transactions 94-D(1):51-59 (2011)
to dblp by dblp on Jan 12, 2011, 12:00 AM
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Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating.
Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, and Masaaki Kondo ASP-DAC, page 369-370. IEEE, (2010)
to dblp by dblp on Dec 26, 2010, 12:00 AM
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Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs.
Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, and Hideharu Amano NOCS, page 61-68. IEEE Computer Society, (2010)
to dblp by dblp on Sep 2, 2010, 12:00 AM
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Adaptive power gating for function units in a microprocessor.
Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, and Hiroshi Nakamura ISQED, page 29-37. IEEE, (2010)
to dblp by dblp on Jul 21, 2010, 4:00 PM
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A fine-grain dynamic sleep control scheme in MIPS R3000.
Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, and Hiroshi Nakamura ICCD, page 612-617. IEEE, (2008)
to dblp by dblp on Apr 21, 2009, 12:00 AM
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Developmental learning of complex syntactical song in the Bengalese finch: A neural network model.
Yuichi Yamashita, Miki Takahasi, Tetsu Okumura, Maki Ikebuchi, Hiroko Yamada, Madoka Suzuki, Kazuo Okanoya, and Jun Tani Neural Networks 21(9):1224-1231 (2008)
to dblp by dblp on Jan 13, 2009, 12:00 AM
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