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publications

(187)

• FPGA implementation of a vehicle detection algorithm using three-dimensional information.
  Masanori Hariyama and Kensaku Yamashita and Michitaka Kameyama IPDPS 1-5 (2008)
  to dblp by dblp on 2008-10-31 00:00:00
  | URL | BibTeX  
• A Direct Algorithm for Multi-valued Bounded Model Checking.
  Jefferson O. Andrade and Yukiyoshi Kameyama ATVA 80-94 (2008)
  to dblp by dblp on 2008-10-21 00:00:00
  | URL | BibTeX  
• Undecidability of Type-Checking in Domain-Free Typed Lambda-Calculi with Existence.
  Koji Nakazawa and Makoto Tatsuta and Yukiyoshi Kameyama and Hiroshi Nakano CSL 478-492 (2008)
  to dblp by dblp on 2008-10-20 00:00:00
  | URL | BibTeX  
• Calculi of meta-variables.
  Masahiko Sato and Takafumi Sakurai and Yukiyoshi Kameyama and Atsushi Igarashi Frontiers of Computer Science in China 2 12-21 (2008)
  to dblp by dblp on 2008-09-25 00:00:00
  | URL | BibTeX  
• Khmer POS Tagger: A Transformation-based Approach with Hybrid Unknown Word Handling.
  Chenda Nou and Wataru Kameyama ICSC 482-492 (2007)
  to dblp by dblp on 2008-09-21 00:00:00
  | URL | BibTeX  
• Common inhibitory mechanism in human inferior prefrontal cortex revealed by event-related functional NRI
  S. Konishi and K. Nakajima and I. Uchida and H. Kikyo and M. Kameyama and Y. Miyashita Brain 122 981-991 (1999)
  to CCP JRR, PFC, WM, inhibition, neuroimaging, by brian.mingus on 2008-09-16 23:39:07
  | BibTeX  
• Transient activation of inferior prefrontal cortex during cognitive set shifting.
  S. Konishi and K. Nakajima and I. Uchida and M. Kameyama and K. Nakahara and K. Sekihara and Y. Miyashita Nature Neuroscience 1 80-84 (1998)
  to CCP JRR, by brian.mingus on 2008-09-16 23:39:07
  | BibTeX  
• Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling.
  Masanori Hariyama and Naoto Yokoyama and Michitaka Kameyama IEICE Transactions 91-C 479-486 (2008)
  to dblp by dblp on 2008-09-16 00:00:00
  | URL | BibTeX  
• Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment.
  Hasitha Muthumala Waidyasooriya and Weisheng Chong and Masanori Hariyama and Michitaka Kameyama IEICE Transactions 91-C 517-525 (2008)
  to dblp by dblp on 2008-09-16 00:00:00
  | URL | BibTeX  
• Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation.
  Tasuku Ito and Michitaka Kameyama ISMVL 39 (2007)
  to dblp by dblp on 2008-09-03 00:00:00
  | URL | BibTeX