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publications

(13)

• A Hardware Algorithm for the Minimum p-Quasi Clique Cover Problem.
  Shuichi Watanabe and Junji Kitamichi and Kenichi Kuroda FPL 139-144 (2007)
  to dblp by dblp on 2008-11-17 00:00:00
  | URL | BibTeX  
• Dynamic Module Library for System Level Modeling and Simulation of Dynamically Reconfigurable Systems.
  Kenji Asano and Junji Kitamichi and Kenichi Kuroda JCP 3 55-62 (2008)
  to dblp by dblp on 2008-08-12 00:00:00
  | URL | BibTeX  
• A Modeling of a Dynamically Reconfigurable Processor Using SystemC.
  Junji Kitamichi and Koji Ueda and Kenichi Kuroda VLSI Design 91-96 (2008)
  to dblp by dblp on 2008-04-03 00:00:00
  | URL | BibTeX  
• A gradual neural-network algorithm for jointly time-slot/code assignment problems in packet radio networks.
  Nobuo Funabiki and Junji Kitamichi IEEE Transactions on Neural Networks 9 1523-1528 (1998)
  to dblp by dblp on 2008-02-15 00:00:00
  | URL | BibTeX  
• Proposal of Dynamic Module Library for System Level Modeling and Simulation of Dynamically Reconfigurable Systems.
  Kenji Asano and Junji Kitamichi and Kenichi Kuroda VLSI Design 373-378 (2007)
  to dblp by dblp on 2007-03-26 00:00:00
  | URL | BibTeX  
• A Conformance Testing Method for Communication Protocols Modeled as Concurrent DFSMs.
  Atsushi Fukada and Akio Nakata and Junji Kitamichi and Teruo Higashino and Ana R. Cavalli ICOIN 155-162 (2001)
  to dblp by dblp on 2006-05-11 00:00:00
  | URL | BibTeX  
• An evolutionary neural network approach for module orientation problems.
  Nobuo Funabiki and Junji Kitamichi and Seishi Nishikawa IEEE Transactions on Systems, Man, and Cybernetics, Part B 28 849-855 (1998)
  to dblp by dblp on 2006-04-21 00:00:00
  | URL | BibTeX  
• A Master-Slave Adaptive Load-Distribution Processor Model on PCA.
  Toshiyuki Ito and Junji Kitamichi and Kenichi Kuroda and Yuichi Okuyama IPDPS (2005)
  to dblp by dblp on 2005-05-06 00:00:00
  | URL | BibTeX  
• Formal Verification Method for Combinatorial Circuits at High Level Design.
  Junji Kitamichi and Hiroyuki Kageyama and Nobuo Funabiki ASP-DAC 319- (1999)
  to dblp by dblp on 2004-08-27 00:00:00
  | URL | BibTeX  
• Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution.
  Takashi Takenaka and Junji Kitamichi and Teruo Higashino and Kenichi Taniguchi ASP-DAC 177-180 (1999)
  to dblp by dblp on 2004-08-27 00:00:00
  | URL | BibTeX