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A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms.
Jose Flich, Tor Skeie, Andres Mejia, Olav Lysne, Pedro López, Antonio Robles, José Duato, Michihiro Koibuchi, Tomas Rokicki, and José Carlos Sancho IEEE Trans. Parallel Distrib. Syst. 23(3):405-425 (2012)
to dblp by dblp on Feb 7, 2012, 12:00 AM
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Statistical Combination of Spatial Interpolation and Multispectral Remote Sensing for Shallow Water Bathymetry.
Ariyo Kanno, Yukio Koibuchi, and Masahiko Isobe IEEE Geosci. Remote Sensing Lett. 8(1):64-67 (2011)
to dblp by dblp on Jan 19, 2012, 12:00 AM
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Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects.
Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, and Hideharu Amano ICNC, page 50-57. IEEE Computer Society, (2011)
to dblp by dblp on Jan 17, 2012, 12:00 AM
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An Efficient Path Setup for a Photonic Network-on-Chip.
Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, and Tsutomu Yoshinaga ICNC, page 156-161. IEEE Computer Society, (2010)
to dblp by dblp on Jan 17, 2012, 12:00 AM
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An Efficient Path Setup for a Hybrid Photonic Network-on-Chip.
Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, and Tsutomu Yoshinaga IJNC 1(2):244-259 (2011)
to dblp by dblp on Dec 12, 2011, 12:00 AM
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Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster.
Michihiro Koibuchi, Konosuke Watanabe, Tomohiro Otsuka, and Hideharu Amano IEEE Trans. Parallel Distrib. Syst. 16(8):747-759 (2005)
to dblp by dblp on Nov 3, 2011, 12:00 AM
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Performance Analysis of ClearSpeed's CSX600 Interconnects.
Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, and Hideharu Amano ISPA, page 203-210. IEEE, (2009)
to dblp by dblp on Sep 8, 2011, 12:00 AM
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A Regular Expression Processor Embedded in Service-Friendly Router for Future Internet.
Yasutsugu Nagatomi, Michihiro Koibuchi, Hideyuki Kawashima, Koichi Inoue, and Hiroaki Nishi ICPP Workshops, page 82-88. IEEE Computer Society, (2010)
to dblp by dblp on Aug 24, 2011, 12:00 AM
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A vertical bubble flow network using inductive-coupling for 3-D CMPs.
Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, and Hideharu Amano NOCS, page 49-56. IEEE Computer Society, (2011)
to dblp by dblp on Aug 12, 2011, 12:00 AM
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A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet.
Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, and Hideharu Amano IEEE Trans. Parallel Distrib. Syst. 22(2):217-230 (2011)
to dblp by dblp on Aug 8, 2011, 12:00 AM
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Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array.
Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, and Katsunobu Nishimura EUC, volume 3207 of Lecture Notes in Computer Science, page 301-311. Springer, (2004)
to dblp by dblp on Aug 4, 2011, 12:00 AM
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Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors.
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, and Tsutomu Yoshinaga IEEE Trans. Computers 60(6):783-799 (2011)
to dblp by dblp on May 29, 2011, 12:00 AM
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Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs.
Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, and Hideharu Amano IEEE Trans. on CAD of Integrated Circuits and Systems 30(4):520-533 (2011)
to dblp by dblp on Apr 20, 2011, 12:00 AM
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Dynamic Resource Allocation and QoS Control Capabilities of the Japanese Academic Backbone Network.
Shigeo Urushidani, Kensuke Fukuda, Michihiro Koibuchi, Motonori Nakamura, Shunji Abe, Yusheng Ji, Michihiro Aoki, and Shigeki Yamada Future Internet 2(3):295-307 (2010)
to dblp by dblp on Feb 8, 2011, 12:00 AM
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An On/Off Link Activation Method for Power Regulation in InfiniBand.
José Miguel Montañana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, and Hideharu Amano PDPTA, page 289-295. CSREA Press, (2009)
to dblp by dblp on Feb 2, 2011, 12:00 AM
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Balanced Dimension-Order Routing for k-ary n-cubes.
José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, and Hideharu Amano ICPP Workshops, page 499-506. IEEE Computer Society, (2009)
to dblp by dblp on Feb 2, 2011, 12:00 AM
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Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks.
José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, and Hideharu Amano NAS, page 218-227. IEEE Computer Society, (2010)
to dblp by dblp on Feb 2, 2011, 12:00 AM
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An analytical network performance model for SIMD processor CSX600 interconnects.
Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, and Hideharu Amano Journal of Systems Architecture - Embedded Systems Design 57(1):146-159 (2011)
to dblp by dblp on Jan 9, 2011, 12:00 AM
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Hardware Architecture for Supporting High-speed Database Insertion on Service-oriented Router for Future Internet.
Tomoaki Makino, Koichi Inoue, Michihiro Koibuchi, Hideyuki Kawashima, and Hiroaki Nishi PDPTA, page 402-407. CSREA Press, (2010)
to dblp by dblp on Dec 7, 2010, 12:00 AM
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Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs.
Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, and Hideharu Amano NOCS, page 61-68. IEEE Computer Society, (2010)
to dblp by dblp on Sep 2, 2010, 12:00 AM
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