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publications

(81)

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Exploring the limits of GPGPU scheduling in control flow bound applications.
Roman Malits, Evgeny Bolotin, Avinoam Kolodny, and Avi Mendelson TACO 8(4):29 (2012)
to dblp by dblp on Feb 7, 2012, 12:00 AM
URL | BibTeX
The complexity of VLSI power-delay optimization by interconnect resizing.
Konstantin Moiseev, Avinoam Kolodny, and Shmuel Wimer J. Comb. Optim. 23(2):292-300 (2012)
to dblp by dblp on Feb 3, 2012, 12:00 AM
URL | BibTeX
Task Scheduling Based On Thread Essence and Resource Limitations.
Tomer Y. Morad, Avinoam Kolodny, and Uri C. Weiser JCP 7(1):53-64 (2012)
to dblp by dblp on Feb 3, 2012, 12:00 AM
URL | BibTeX
Efficiency optimization of integrated DC-DC buck converters.
Gregory Sizikov, Avinoam Kolodny, Eby G. Friedman, and Michael Zelikson ICECS, page 1208-1211. IEEE, (2010)
to dblp by dblp on Nov 29, 2011, 12:00 AM
URL | BibTeX
Memristor-based IMPLY logic design procedure.
Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, and Eby G. Friedman ICCD, page 142-147. IEEE, (2011)
to dblp by dblp on Nov 23, 2011, 12:00 AM
URL | BibTeX
A Cost Effective Centralized Adaptive Routing for Networks-on-Chip.
Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, and Shmuel Wimer DSD, page 39-46. IEEE, (2011)
to dblp by dblp on Nov 21, 2011, 12:00 AM
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Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints.
Yoni Aizik, and Avinoam Kolodny VLSI Design (2011)
to dblp by dblp on Nov 3, 2011, 12:00 AM
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Centralized Adaptive Routing for NoCs.
Ran Manevich, Israel Cidon, Avinoam Kolodny, and Isask'har Walter Computer Architecture Letters 9(2):57-60 (2010)
to dblp by dblp on Oct 25, 2011, 12:00 AM
URL | BibTeX
Many-Core vs. Many-Thread Machines: Stay Away From the Valley.
Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, and Uri C. Weiser Computer Architecture Letters 8(1):25-28 (2009)
to dblp by dblp on Oct 25, 2011, 12:00 AM
URL | BibTeX
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP.
I. Walter, Israel Cidon, and Avinoam Kolodny Computer Architecture Letters 7(2):61-64 (2008)
to dblp by dblp on Oct 25, 2011, 12:00 AM
URL | BibTeX
Nahalal: Cache Organization for Chip Multiprocessors.
Zvika Guz, Idit Keidar, Avinoam Kolodny, and Uri C. Weiser Computer Architecture Letters 6(1):21-24 (2007)
to dblp by dblp on Oct 25, 2011, 12:00 AM
URL | BibTeX
NoCs simulation framework for OMNeT++.
Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, and Avinoam Kolodny NOCS, page 265-266. IEEE Computer Society, (2011)
to dblp by dblp on Aug 12, 2011, 12:00 AM
URL | BibTeX
Delay analysis of wormhole based heterogeneous NoC.
Yaniv Ben-Itzhak, Israel Cidon, and Avinoam Kolodny NOCS, page 161-168. IEEE Computer Society, (2011)
to dblp by dblp on Aug 12, 2011, 12:00 AM
URL | BibTeX
An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm.
Salomon Beer, Ran Ginosar, Michael Priel, Rostislav Reuven Dobkin, and Avinoam Kolodny ISCAS, page 2593-2596. IEEE, (2011)
to dblp by dblp on Jul 7, 2011, 12:00 AM
URL | BibTeX
Network Delays and Link Capacities in Application-Specific Wormhole NoCs.
Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, and Avinoam Kolodny VLSI Design (2007)
to dblp by dblp on Jul 6, 2011, 12:00 AM
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The Devolution of Synchronizers.
Salomon Beer, Ran Ginosar, Michael Priel, Rostislav Reuven Dobkin, and Avinoam Kolodny ASYNC, page 94-103. IEEE Computer Society, (2010)
to dblp by dblp on Jun 9, 2011, 12:00 AM
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Threads vs. caches: Modeling the behavior of parallel workloads.
Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, and Uri C. Weiser ICCD, page 274-281. IEEE, (2010)
to dblp by dblp on May 26, 2011, 12:00 AM
URL | BibTeX
Static timing analysis for modeling QoS in networks-on-chip.
Evgeni Krimer, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter, and Mattan Erez J. Parallel Distrib. Comput. 71(5):687-699 (2011)
to dblp by dblp on Apr 26, 2011, 12:00 AM
URL | BibTeX
Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect.
Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, and Avinoam Kolodny IEEE Trans. VLSI Syst. 18(5):689-696 (2010)
to dblp by dblp on Feb 15, 2011, 12:00 AM
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Asynchronous Current Mode Serial Communication.
Rostislav Reuven Dobkin, Michael Moyal, Avinoam Kolodny, and Ran Ginosar IEEE Trans. VLSI Syst. 18(7):1107-1117 (2010)
to dblp by dblp on Feb 15, 2011, 12:00 AM
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