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A Novel Force Modeling Scheme for Needle Insertion Using Multiple Kalman Filters.
Ali Asadian, Mehrdad R. Kermani, and Rajni V. Patel IEEE T. Instrumentation and Measurement 61(2):429-438 (2012)
to dblp by dblp on Feb 13, 2012, 12:00 AM
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Spatially resolved Halpha maps and sizes of 57 strongly star-forming galaxies at z~1 from 3D-HST: evidence for rapid inside-out assembly of disk galaxies
Erica June Nelson, Pieter G. van Dokkum, Gabriel Brammer, Natascha Forster Schreiber, Marijn Franx, Mattia Fumagalli, Shannon Patel, Hans-Walter Rix, Rosalind E. Skelton, Rachel Bezanson, Elisabete Da Cunha, Mariska Kriek, Ivo Labbe, Britt Lundgren, Ryan Quadri, and Kasper B. Schmidt (2012)cite arxiv:1202.1822 Comment: ApJ Letters, in press. The public 3D-HST website is http://3dhst.research.yale.edu/Home.html .
to Ha disk size by miki on Feb 10, 2012, 7:08 PM
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An optimization based approach to the partial scan design problem.
Vivek Chickermane, and Janak H. Patel ITC, page 377-386. IEEE Computer Society, (1990)
to dblp by dblp on Feb 9, 2012, 12:00 AM
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Towards a Multi-MoC Hardware/Software Co-design Framework Using Abstract State Machines.
Nathan Buchanan, and Hiren D. Patel MTV, page 53-58. IEEE, (2010)
to dblp by dblp on Feb 9, 2012, 12:00 AM
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Analytical model based on green criteria for optical backbone network interconnection.
José M. Gutiérrez López, Tahir M. Riaz, Jens Myrup Pedersen, Ahmed Patel, and Ole Brun Madsen Computer Standards & Interfaces 33(6):574-586 (2011)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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Stuck-at fault: a fault model for the next millennium.
Janak H. Patel ITC, page 1166. (1997)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment.
Phil Nigh, David P. Vallett, Atul Patel, Jason Wright, Franco Motika, Donato O. Forlenza, Ray Kurtulik, and Wendy Chong ITC, page 1152-1161. IEEE Computer Society, (1999)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment.
Phil Nigh, David P. Vallett, Atul Patel, and Jason Wright ITC, page 43-52. IEEE Computer Society, (1998)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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Compact two-pattern test set generation for combinational and full scan circuits.
Ilker Hamzaoglu, and Janak H. Patel ITC, page 944-953. IEEE Computer Society, (1998)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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Putting the Squeeze on Test Sequences.
Elizabeth M. Rudnick, and Janak H. Patel ITC, page 723-732. IEEE Computer Society, (1997)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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BART: A Bridging Fault Test Generation for Sequential Circuits.
James P. Cusey, and Janak H. Patel ITC, page 838-847. IEEE Computer Society, (1997)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information.
Dong Xiang, and Janak H. Patel ITC, page 548-557. IEEE Computer Society, (1996)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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On Potential Fault Detection in Sequential Circuits.
Elizabeth M. Rudnick, Janak H. Patel, and Irith Pomeranz ITC, page 142-149. IEEE Computer Society, (1996)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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Testability Features of the SuperSPARCtm.
Rajiv Patel, and Krishna Yarlagadda ITC, page 773-781. IEEE Computer Society, (1993)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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Fast and Accurate CMOS Bridging Fault Simulation.
Jeff Rearick, and Janak H. Patel ITC, page 54-62. IEEE Computer Society, (1993)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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An Instruction Sequence Assembling Methodology for Testing Microprocessors.
Jaushin Lee, and Janak H. Patel ITC, page 49-58. IEEE Computer Society, (1992)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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Diagnostic Fault Simulation of Sequential Circuits.
Elizabeth M. Rudnick, W. Kent Fuchs, and Janak H. Patel ITC, page 178-186. IEEE Computer Society, (1992)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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Design for Testability Using Architectural Descriptions.
Vivek Chickermane, Jaushin Lee, and Janak H. Patel ITC, page 752-761. IEEE Computer Society, (1992)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults.
Jaushin Lee, and Janak H. Patel ITC, page 729-738. IEEE Computer Society, (1991)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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Enhanced delay defect coverage with path-segments.
Manish Sharma, and Janak H. Patel ITC, page 385-392. IEEE Computer Society, (2000)
to dblp by dblp on Feb 8, 2012, 12:00 AM
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