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XOR and backpropagation learning: in and out of the chaos?
Koen Bertels, Luc Neuberg, Stamatis Vassiliadis, and D. G. Pechanek ESANN, (1995)
to dblp by dblp on Feb 2, 2012, 12:00 AM
URL | BibTeX
ManArray Processor Interconnection Network: An Introduction.
Gerald G. Pechanek, Stamatis Vassiliadis, and Nikos Pitsianis Euro-Par, volume 1685 of Lecture Notes in Computer Science, page 761-765. Springer, (1999)
to dblp by dblp on Jun 20, 2011, 12:00 AM
URL | BibTeX
Chaos and Neural Network Learning. Some Observations.
Koen Bertels, Luc Neuberg, Stamatis Vassiliadis, and D. G. Pechanek Neural Processing Letters 7(2):69-80 (1998)
to dblp by dblp on May 31, 2011, 12:00 AM
URL | BibTeX
On Chaos and Neural Networks: The Backpropagation Paradigm.
Koen Bertels, Luc Neuberg, Stamatis Vassiliadis, and D. G. Pechanek Artif. Intell. Rev. 15(3):165-187 (2001)
to dblp by dblp on May 19, 2011, 12:00 AM
URL | BibTeX
A neuro-emulator with embedded capabilities for generalized learning.
Valentine C. Aikens II, José G. Delgado-Frias, Gerald G. Pechanek, and Stamatis Vassiliadis Journal of Systems Architecture 45(14):1219-1243 (1999)
to dblp by dblp on Sep 15, 2009, 12:00 AM
URL | BibTeX
The Sum-Absolute-Difference Motion Estimation Accelerato.
Stamatis Vassiliadis, Edwin A. Hakkennes, J. S. S. M. Wong, and Gerald G. Pechanek EUROMICRO, page 20559-20566. IEEE Computer Society, (1998)
to dblp by dblp on Aug 6, 2008, 12:00 AM
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Indirect VLIW memory allocation for the ManArray multiprocessor DSP.
Nikos Pitsianis, and Gerald G. Pechanek SIGARCH Computer Architecture News 31(1):69-74 (2003)
to dblp by dblp on Apr 5, 2006, 12:00 AM
URL | BibTeX
A Neuro-Architecture with Embedded Learning.
Valentine C. Aikens II, Steven M. Barber, José G. Delgado-Frias, Gerald G. Pechanek, and Stamatis Vassiliadis Parallel and Distributed Computing and Systems, page 103-106. IASTED/ACTA Press, (1995)
to dblp by dblp on Jul 14, 2004, 12:00 AM
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The ManArray Embedded Processor Architecture.
Gerald G. Pechanek, and Stamatis Vassiliadis EUROMICRO, page 1348-1355. IEEE Computer Society, (2000)
to dblp by dblp on Sep 24, 2003, 12:00 AM
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Architectural simulation system for M.f.a.s.t.
Chris H. L. Moller, and Gerald G. Pechanek Annual Simulation Symposium, page 221-. IEEE Computer Society, (1996)
to dblp by dblp on Aug 27, 2003, 12:00 AM
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A 90k Gate ``CLB'' for Parallel Distributed Computing.
Bruce Schulman, and Gerald G. Pechanek IPDPS Workshops, volume 1800 of Lecture Notes in Computer Science, page 831-838. Springer, (2000)
to dblp by dblp on Jun 13, 2002, 12:00 AM
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MFAST: a single chip highly parallel image processing architecture.
Gerald G. Pechanek, M. Stojancic, Stamatis Vassiliadis, and C. John Glossner ICIP, page 69-72. (1995)
to dblp by dblp on Mar 18, 2002, 12:00 AM
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