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Implementation of a Reverse Time Migration kernel using the HCE High Level Synthesis tool.
Tassadaq Hussain, Miquel Pericàs, Nacho Navarro, and Eduard Ayguadé FPT, page 1-8. IEEE, (2011)
to dblp by dblp on Jan 25, 2012, 12:00 AM
URL | BibTeX
Assessing Accelerator-Based HPC Reverse Time Migration.
Mauricio Araya-Polo, Javier Cabezas, Mauricio Hanzich, Miquel Pericàs, Félix Rubio, Isaac Gelado, Muhammad Shafiq, Enric Morancho, Nacho Navarro, Eduard Ayguadé, José María Cela, and Mateo Valero IEEE Trans. Parallel Distrib. Syst. 22(1):147-162 (2011)
to dblp by dblp on Aug 8, 2011, 12:00 AM
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with Wide Functional Units.
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, and Mateo Valero SAMOS, volume 3133 of Lecture Notes in Computer Science, page 88-97. Springer, (2004)
to dblp by dblp on Jul 7, 2011, 12:00 AM
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Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes.
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, and Mateo Valero ISHPC, volume 2858 of Lecture Notes in Computer Science, page 113-126. Springer, (2003)
to dblp by dblp on Jul 5, 2011, 12:00 AM
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FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators.
Muhammad Shafiq, Miquel Pericàs, Nacho Navarro, and Eduard Ayguadé FPL, page 568-573. IEEE, (2010)
to dblp by dblp on Jan 24, 2011, 12:00 AM
URL | BibTeX
A Two-Level Load/Store Queue Based on Execution Locality.
Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Alexander V. Veidenbaum, Daniel A. Jiménez, and Mateo Valero ISCA, page 25-36. IEEE, (2008)
to dblp by dblp on Jan 6, 2010, 12:00 AM
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A decoupled KILO-instruction processor.
Miquel Pericàs, Adrián Cristal, Ruben Gonzalez, Daniel A. Jiménez, and Mateo Valero HPCA, page 53-64. IEEE Computer Society, (2006)
to dblp by dblp on Feb 26, 2009, 12:00 AM
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Power-efficient VLIW design using clustering and widening.
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, and Mateo Valero IJES 3(3):141-149 (2008)
to dblp by dblp on Nov 13, 2008, 12:00 AM
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A Flexible Heterogeneous Multi-Core Architecture.
Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Ruben Gonzalez, Daniel A. Jiménez, and Mateo Valero PACT, page 13-24. IEEE Computer Society, (2007)
to dblp by dblp on Aug 20, 2008, 12:00 AM
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High-performance and low-power VLIW cores for numerical computations.
Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, and Mateo Valero IJHPCN 1(4):171-179 (2004)
to dblp by dblp on Jan 2, 2008, 12:00 AM
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An Optimized Front-End Physical Register File with Banking and Writeback Filtering.
Miquel Pericàs, Rubén González, Adrián Cristal, Alexander V. Veidenbaum, and Mateo Valero PACS, volume 3471 of Lecture Notes in Computer Science, page 1-14. Springer, (2004)
to dblp by dblp on Mar 28, 2007, 12:00 AM
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Kilo-Instruction Processors: Overcoming the Memory Wall.
Adrián Cristal, Oliverio J. Santana, Francisco Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, and Mateo Valero IEEE Micro 25(3):48-57 (2005)
to dblp by dblp on Nov 15, 2006, 12:00 AM
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An asymmetric clustered processor based on value content.
Rubén González, Adrián Cristal, Miquel Pericàs, Mateo Valero, and Alexander V. Veidenbaum ICS, page 61-70. ACM, (2005)
to dblp by dblp on Feb 13, 2006, 12:00 AM
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