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Tensor Versus Matrix Completion: A Comparison With Application to Spectral Data.
Marco Signoretto, Raf Van de Plas, Bart De Moor, and Johan A. K. Suykens IEEE Signal Process. Lett. 18(7):403-406 (2011)
to dblp by dblp on Feb 6, 2012, 12:00 AM
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A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS.
Pierluigi Nuzzo, Claudio Nani, Costantino Armiento, Alberto L. Sangiovanni-Vincentelli, Jan Craninckx, and Geert Van der Plas IEEE Trans. on Circuits and Systems 59-I(1):80-92 (2012)
to dblp by dblp on Feb 1, 2012, 12:00 AM
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A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS.
Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, and Geert Van der Plas J. Solid-State Circuits 45(10):2080-2090 (2010)
to dblp by dblp on Jan 9, 2012, 12:00 AM
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Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS.
Lynn Bos, Gerd Vandersteen, Pieter Rombouts, Arnd Geis, Alonso Morgado, Yves Rolain, Geert Van der Plas, and Julien Ryckaert J. Solid-State Circuits 45(6):1198-1208 (2010)
to dblp by dblp on Jan 9, 2012, 12:00 AM
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A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS.
Pieter Crombez, Geert Van der Plas, Michiel Steyaert, and Jan Craninckx J. Solid-State Circuits 45(6):1159-1171 (2010)
to dblp by dblp on Jan 9, 2012, 12:00 AM
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Automatic Keyword Extraction from Spoken Text. A Comparison of two Lexical Resources: the EDR and WordNet
Lonneke van der Plas, Vincenzo Pallotta, Martin Rajman, and Hatem Ghorbel CoRR (2004)
to dblp by dblp on Dec 5, 2011, 12:00 AM
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Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance
Charlotte Soens, Geert Van der Plas, Piet Wambacq, and Stéphane Donnay CoRR (2007)
to dblp by dblp on Dec 5, 2011, 12:00 AM
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Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures.
Pierluigi Nuzzo, Fernando De Bernardinis, Pierangelo Terreni, and Geert Van der Plas IEEE Trans. on Circuits and Systems 55-I(6):1441-1454 (2008)
to dblp by dblp on Nov 4, 2011, 12:00 AM
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DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow.
Dragomir Milojevic, Herman Oprins, Julien Ryckaert, Paul Marchal, and Geert Van der Plas CICC, page 1-4. IEEE, (2011)
to dblp by dblp on Oct 30, 2011, 12:00 AM
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A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems.
Stephane Bronckers, Karen Scheir, Geert Van der Plas, Gerd Vandersteen, and Yves Rolain IEEE Trans. on CAD of Integrated Circuits and Systems 28(11):1613-1626 (2009)
to dblp by dblp on Oct 19, 2011, 12:00 AM
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A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS.
Lynn Bos, Gerd Vandersteen, Julien Ryckaert, Pieter Rombouts, Yves Rolain, and Geert Van der Plas ISSCC, page 176-177. IEEE, (2009)
to dblp by dblp on Oct 19, 2011, 12:00 AM
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Fine grain thermal modeling and experimental validation of 3D-ICs.
Herman Oprins, A. Srinivasan, Miroslav Cupák, Vladimir Cherman, Cristina Torregiani, Michele Stucchi, Geert Van der Plas, Paul Marchal, Bart Vandevelde, and E. Cheng Microelectronics Journal 42(4):572-578 (2011)
to dblp by dblp on Oct 18, 2011, 12:00 AM
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Design issues and considerations for low-cost 3D TSV IC technology.
Geert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, and Eric Beyne ISSCC, page 148-149. IEEE, (2010)
to dblp by dblp on Oct 18, 2011, 12:00 AM
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A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS.
Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, and Geert Van der Plas ISSCC, page 296-297. IEEE, (2010)
to dblp by dblp on Oct 18, 2011, 12:00 AM
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Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.
Geert Van der Plas, Steven Thijs, Dimitri Linten, Guruprasad Katti, Paresh Limaye, Abdelkarim Mercha, Michele Stucchi, Herman Oprins, Bart Vandevelde, Nikolaos Minas, Miro Cupac, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Eric Beyne, and Paul Marchal CICC, page 1-4. IEEE, (2010)
to dblp by dblp on Sep 23, 2011, 12:00 AM
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3D heterogeneous system integration: application driver for 3D technology development.
Eric Beyne, Pol Marchal, and Geert Van der Plas DAC, page 213. ACM, (2011)
to dblp by dblp on Sep 6, 2011, 12:00 AM
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An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations.
Geert Eneman, J. Cho, V. Moroz, Dragomir Milojevic, M. Choi, Kristin De Meyer, Abdelkarim Mercha, Eric Beyne, Thomas Hoffmann, and Geert Van der Plas DATE, page 505-506. IEEE, (2011)
to dblp by dblp on Sep 2, 2011, 12:00 AM
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3D integration: Circuit design, test, and reliability challenges.
Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, and Pol Marchal IOLTS, page 217. IEEE, (2010)
to dblp by dblp on Aug 30, 2011, 12:00 AM
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The 4GPLUS Project, Overview and Main Results.
Dirk-Jaap Plas, Mortaza S. Bargh, Jan Laarhuis, Jeroen van Vugt, Jacco Brok, and Herma Van Kranenburg ECUMN, volume 3262 of Lecture Notes in Computer Science, page 1-11. Springer, (2004)
to dblp by dblp on Aug 10, 2011, 12:00 AM
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Validation of the Open Service Access API for UMTS Application Provisioning.
Maarten Wegdam, Dirk-Jaap Plas, and Musa R. Unmehopa PROMS, volume 2213 of Lecture Notes in Computer Science, page 210-221. Springer, (2001)
to dblp by dblp on Jun 28, 2011, 12:00 AM
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