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(2)

• A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technology.
  Varna Puvvada and S. Potla and S. Tamizh Selvam and P. R. Suresh VLSI Design 192- (1995)
  to dblp by dblp on 2005-02-25 00:00:00
  | URL | BibTeX  
• Combined Effect of Grain Boundary Depletion and PolySi/Oxide Interface Depletion on Drain Characteristics of a p-MOSFET.
  R. P. Suresh and P. Venugopal and S. Tamizh Selvam and S. Potla VLSI Design 156-161 (1996)
  to dblp by dblp on 2005-02-23 00:00:00
  | URL | BibTeX