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(27)

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Pushing the limits of digital imaging using structured illumination.
Prasanna Rangarajan, Indranil Sinharoy, Panos Papamichalis, and Marc P. Christensen ICCV, page 1315-1322. IEEE, (2011)
to dblp by dblp on Jan 19, 2012, 12:00 AM
URL | BibTeX
The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor.
Dieter F. Wendel, Ronald N. Kalla, Robert Cargoni, Joachim G. Clabes, Joshua Friedrich, R. Frech, James A. Kahle, Balaram Sinharoy, William J. Starke, Scott Taylor, Steve Weitzel, Sam G. Chu, Md. Saiful Islam, and Victor V. Zyuban ISSCC, page 102-103. IEEE, (2010)
to dblp by dblp on Oct 19, 2011, 12:00 AM
URL | BibTeX
Design and implementation of the POWER5 microprocessor.
Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip Restle, Ronald N. Kalla, Joseph McGill, and J. Steve Dodson DAC, page 670-672. ACM, (2004)
to dblp by dblp on Oct 19, 2011, 12:00 AM
URL | BibTeX
Compiler optimization to improve data locality for processor multithreading.
Balaram Sinharoy Scientific Programming 7(1):21-37 (1999)
to dblp by dblp on Sep 12, 2011, 12:00 AM
URL | BibTeX
Data and Task Alignment in Distributed Memory Architectures.
Balaram Sinharoy, and Boleslaw K. Szymanski J. Parallel Distrib. Comput. 21(1):61-74 (1994)
to dblp by dblp on Sep 9, 2011, 12:00 AM
URL | BibTeX
Complexity of the Closest Vector Problem in a Lattice Generated by 0, 1-Matrix.
Boleslaw K. Szymanski, and Balaram Sinharoy Inf. Process. Lett. 42(3):121-126 (1992)
to dblp by dblp on Jul 8, 2011, 12:00 AM
URL | BibTeX
Corrigenda: Complexity of the Closest Vector Problem in a Lattice Generated by 0, 1-Matrix.
Boleslaw K. Szymanski, and Balaram Sinharoy Inf. Process. Lett. 43(3):167 (1992)
to dblp by dblp on Jul 8, 2011, 12:00 AM
URL | BibTeX
Optimized Thread Creation for Processor Multithreading.
Balaram Sinharoy Comput. J. 40(6):388-400 (1997)
to dblp by dblp on Jun 28, 2011, 12:00 AM
URL | BibTeX
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors.
Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Richard J. Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, and Joel M. Tendler HPCA, page 238-242. IEEE Computer Society, (2005)
to dblp by dblp and 1 other user on May 24, 2011, 12:00 AM
URL | BibTeX
Adapting Game-Playing Agents to Game Requirements.
Joshua Jones, Chris Parnin, Avik Sinharoy, Spencer Rugaber, and Ashok K. Goel AIIDE, The AAAI Press, (2009)
to dblp by dblp on Aug 18, 2010, 12:00 AM
URL | BibTeX
POWER7 multi-core processor design.
Balaram Sinharoy MICRO, page 1. ACM, (2009)
to dblp by dblp on Jul 21, 2010, 4:01 PM
URL | BibTeX
Power7: IBM's Next-Generation Server Processor.
Ronald N. Kalla, Balaram Sinharoy, William J. Starke, and Michael S. Floyd IEEE Micro 30(2):7-15 (2010)
to dblp by dblp on Jul 21, 2010, 3:46 PM
URL | BibTeX
Model-based region-of-interest estimation for adaptive resource allocation in multi-aperture imaging systems.
Indranil Sinharoy, Scott C. Douglas, Dinesh Rajan, and Marc P. Christensen ICASSP, page 1961-1964. IEEE, (2008)
to dblp by dblp on Feb 5, 2010, 12:00 AM
URL | BibTeX
Efficiency of Data Alignment on Maspar.
William Maniatty, Boleslaw K. Szymanski, and Balaram Sinharoy SIGPLAN Workshop, page 48-51. (1992)
to dblp by dblp on Jan 29, 2010, 12:00 AM
URL | BibTeX
Teleological Software Adaptation.
Joshua Jones, Chris Parnin, Avik Sinharoy, Spencer Rugaber, and Ashok K. Goel SASO, page 198-205. IEEE Computer Society, (2009)
to dblp by dblp on Dec 21, 2009, 12:00 AM
URL | BibTeX
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors
Hans Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor Zyuban, Rick Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, and Joel Tendler HPCA '05: Proceedings of the 11th International Symposium on High-Performance Computer Architecture, page 238--242. Washington, DC, USA, IEEE Computer Society, (2005)
to Clock-Gating PhD_Background_Mechanisms PhD_Biblio by derkling and 1 other user on Aug 31, 2009, 3:54 PM
DOI | BibTeX
Compiler Technology for Parallel Scientific Computation.
Can C. Özturan, Balaram Sinharoy, and Boleslaw K. Szymanski Scientific Programming 3(3):201-225 (1994)
to dblp by dblp on Aug 7, 2008, 12:00 AM
URL | BibTeX
Parallelising Compilers and Systems.
Balaram Sinharoy, and Boleslaw K. Szymanski Parallel Algorithms Appl. 12(1-3):5-20 (1997)
to dblp by dblp on Feb 4, 2008, 12:00 AM
URL | BibTeX
Introduction: Special Issue on Optimising Compilers for Parallel Languages.
Balaram Sinharoy, and Boleslaw K. Szymanski Parallel Algorithms Appl. 12(1-3):1-4 (1997)
to dblp by dblp on Feb 4, 2008, 12:00 AM
URL | BibTeX
Announcement of a Special Issue of the Journal of Parallel Algorithms and Applications on Optimising Compilers for Parallel Languages.
Balaram Sinharoy, and Boleslaw K. Szymanski Parallel Algorithms Appl. 7(3-4):313 (1995)
to dblp by dblp on Feb 4, 2008, 12:00 AM
URL | BibTeX

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