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Image Enhancement Algorithm for Ink-on-Paper Fingerprints.
Raghav Agrawal, Badrinath G. Srinivas, and Phalguni Gupta ICIC 1, volume 6838 of Lecture Notes in Computer Science, page 311-318. Springer, (2011)
to dblp by dblp on Feb 10, 2012, 12:00 AM
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Sequential logic synthesis for testability using register-transfer level descriptions.
Abhijit Ghosh, Srinivas Devadas, and A. Richard Newton ITC, page 274-283. IEEE Computer Society, (1990)
to dblp by dblp on Feb 9, 2012, 12:00 AM
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Direct access test scheme-design of block and core cells for embedded ASICs.
Venkata R. Immaneni, and Srinivas Raman ITC, page 488-492. IEEE Computer Society, (1990)
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Design of integrated circuits fully testable for delay-faults and multifaults.
Srinivas Devadas, and Kurt Keutzer ITC, page 284-293. IEEE Computer Society, (1990)
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Redundancies and Don't Cares in Sequential Logic Synthesis.
Srinivas Devadas, Hi-Keung Tony Ma, and A. Richard Newton ITC, page 491-500. IEEE Computer Society, (1989)
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Delay Test Generation for Synchronous Sequential Circuits.
Srinivas Devadas ITC, page 144-152. IEEE Computer Society, (1989)
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Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment.
Srinivas Patil, and Prithviraj Banerjee ITC, page 718-726. IEEE Computer Society, (1989)
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Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines.
Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, and Alberto L. Sangiovanni-Vincentelli ITC, page 621-630. IEEE Computer Society, (1988)
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An Incomplete Scan Design Approach to Test Generation for Sequential Machines.
Hi-Keung Tony Ma, A. Richard Newton, Srinivas Devadas, and Alberto L. Sangiovanni-Vincentelli ITC, page 730-734. IEEE Computer Society, (1988)
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An algorithmic approach to optimizing fault coverage for BIST logic synthesis.
Srinivas Devadas, and Kurt Keutzer ITC, page 164-173. IEEE Computer Society, (1998)
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Testability, Debuggability, and Manufacturability Features of the UltraSPARCTM-I Microprocessor.
Marc E. Levitt, Srinivas Nori, Sridhar Narayanan, G. P. Grewal, Lynn Youngs, Anjali Jones, Greg Billus, and Siva Paramanandam ITC, page 157-166. IEEE Computer Society, (1995)
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Design of an Efficient Weighted-Random-Pattern Generation System.
Rohit Kapur, Srinivas Patil, Thomas J. Snethen, and Thomas W. Williams ITC, page 491-500. IEEE Computer Society, (1994)
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Skewed-Load Transition Test: Part 2, Coverage.
Srinivas Patil, and Jacob Savir ITC, page 714-722. IEEE Computer Society, (1992)
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A Layout Driven Design for Testability Technique for MOS VLSI Circuits.
Sungho Kim, Prithviraj Banerjee, and Srinivas Patil ITC, page 157-165. IEEE Computer Society, (1991)
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Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks.
Pranav Ashar, Srinivas Devadas, and Kurt Keutzer ITC, page 887-896. IEEE Computer Society, (1991)
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A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits.
Kwang-Ting Cheng, Srinivas Devadas, and Kurt Keutzer ITC, page 403-410. IEEE Computer Society, (1991)
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A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests.
Sungchul Park, Li Chen, Praveen Parvathala, Srinivas Patil, and Irith Pomeranz ITC, page 1-10. IEEE, (2006)
to dblp by dblp on Feb 7, 2012, 12:00 AM
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Modeling habituation in rat EEG-evoked responses via a neural mass model with feedback.
Srinivas Laxminarayan, Gilead Tadmor, Solomon Gilbert Diamond, Eric L. Miller, Maria Angela Franceschini, and Dana H. Brooks Biological Cybernetics 105(5-6):371-397 (2011)
to dblp by dblp on Feb 6, 2012, 12:00 AM
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FIR system identification using higher order cumulants-a generalized approach.
L. Srinivas, and K. V. S. Hari IEEE Transactions on Signal Processing 43(12):3061-3065 (1995)
to dblp by dblp on Feb 5, 2012, 12:00 AM
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Orthogonal decode and forward relaying with improved spectral efficiency.
Kothapalli V. Srinivas, Krishnamurthy Giridhar, and R. David Koilpillai IEEE Communications Letters 13(2):109-111 (2009)
to dblp by dblp on Feb 2, 2012, 12:00 AM
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