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Introduction to the special issue on high-performance and embedded architectures and compilers.
Per Stenström, and Koen De Bosschere TACO 8(4):18 (2012)
to dblp by dblp on Feb 7, 2012, 12:00 AM
URL | BibTeX
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory.
Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, and José M. García PACT, page 203-204. IEEE Computer Society, (2011)
to dblp by dblp on Jan 5, 2012, 12:00 AM
URL | BibTeX
The FAB Predictor: Using Fourier Analysis to Predict the Outcome of Conditional Branches.
Martin Kämpe, Per Stenström, and Michel Dubois HPCA, page 223-232. IEEE Computer Society, (2002)
to dblp by dblp on Jan 3, 2012, 12:00 AM
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A Prefetching Technique for Irregular Accesses to Linked Data Structures.
Magnus Karlsson, Fredrik Dahlgren, and Per Stenström HPCA, page 206-217. IEEE Computer Society, (2000)
to dblp by dblp on Jan 3, 2012, 12:00 AM
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Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors.
Fredrik Dahlgren, and Per Stenström HPCA, page 68-77. IEEE Computer Society, (1995)
to dblp by dblp on Jan 3, 2012, 12:00 AM
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Performance Evaluation of a Cluster-Based Multiprocessor Built from ATM Switches and Bus-Based Multiprocessor Servers.
Magnus Karlsson, and Per Stenström HPCA, page 4-13. IEEE Computer Society, (1996)
to dblp by dblp on Jan 3, 2012, 12:00 AM
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Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms.
Fredrik Warg, and Per Stenström IEEE PACT, page 221-230. IEEE Computer Society, (2001)
to dblp by dblp on Jan 3, 2012, 12:00 AM
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Simple Compiler Algorithms to Reduce Ownership Operhead in Cache Coherence Protocols.
Jonas Skeppstedt, and Per Stenström ASPLOS, page 286-296. ACM Press, (1994)
to dblp by dblp on Dec 23, 2011, 12:00 AM
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Shared-memory multiprocessing: Current state and future directions.
Per Stenström, Erik Hagersten, David J. Lilja, Margaret Martonosi, and Madan Venugopal Advances in Computers (2000)
to dblp by dblp on Nov 29, 2011, 12:00 AM
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The Velox Transactional Memory Stack.
Yehuda Afek, Ulrich Drepper, Pascal Felber, Christof Fetzer, Vincent Gramoli, Michael Hohmuth, Etienne Riviere, Per Stenström, Osman S. Unsal, Walther Maldonado, Derin Harmanci, Patrick Marlier, Stephan Diestelhorst, Martin Pohlack, Adrián Cristal, Ibrahim Hur, Aleksandar Dragojevic, Rachid Guerraoui, Michal Kapalka, Sasa Tomic, Guy Korland, Nir Shavit, Martin Nowack, and Torvald Riegel IEEE Micro 30(5):76-87 (2010)
to dblp by dblp on Nov 3, 2011, 12:00 AM
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Sequential Hardware Prefetching in Shared-Memory Multiprocessors.
Fredrik Dahlgren, Michel Dubois, and Per Stenström IEEE Trans. Parallel Distrib. Syst. 6(7):733-746 (1995)
to dblp by dblp on Nov 3, 2011, 12:00 AM
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Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors.
Fredrik Dahlgren, and Per Stenström IEEE Trans. Parallel Distrib. Syst. 7(4):385-398 (1996)
to dblp by dblp on Nov 3, 2011, 12:00 AM
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Implications of Merging Phases on Scalability of Multi-core Architectures.
Madhavan Manivannan, Ben H. H. Juurlink, and Per Stenström ICPP, page 622-631. IEEE, (2011)
to dblp by dblp on Oct 28, 2011, 12:00 AM
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Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory.
Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, and Per Stenström ICPP, page 73-82. IEEE, (2011)
to dblp by dblp on Oct 28, 2011, 12:00 AM
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Characterization and exploitation of narrow-width loads: the narrow-width cache approach.
Mafijul Md. Islam, and Per Stenström CASES, page 227-236. ACM, (2010)
to dblp by dblp on Oct 21, 2011, 12:00 AM
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A unified approach to eliminate memory accesses early.
Mafijul Md. Islam, and Per Stenström CASES, page 55-64. ACM, (2011)
to dblp by dblp on Oct 20, 2011, 12:00 AM
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Characterising and Modelling Shared Memory Accesses in Multiprocessor Programs.
Mats Brorsson, and Per Stenström Parallel Computing 22(6):869-893 (1996)
to dblp by dblp on Sep 14, 2011, 12:00 AM
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The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems.
Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, and Per Stenström IPDPS Workshops, page 700-707. IEEE, (2011)
to dblp by dblp on Sep 12, 2011, 12:00 AM
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Comparative Evaluation of Latency-Tolerating and -Reducing Techniques for Hardware-Only and Software-Only Directory Protocols.
Håkan Grahn, and Per Stenström J. Parallel Distrib. Comput. 60(7):807-834 (2000)
to dblp by dblp on Sep 9, 2011, 12:00 AM
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Evaluation of a Competitive-Update Cache Coherence Protocol with Migratory Data Detection.
Håkan Grahn, and Per Stenström J. Parallel Distrib. Comput. 39(2):168-180 (1996)
to dblp by dblp on Sep 9, 2011, 12:00 AM
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