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Revisiting the Newton-Raphson Iterative Method for Decimal Division.
Mário P. Véstias, and Horácio C. Neto FPL, page 138-143. IEEE, (2011)
to dblp by dblp on Oct 24, 2011, 12:00 AM
URL | BibTeX
Run-Time Reconfigurable Array Using Magnetic RAM.
Victor Silva, Luís Bica Oliveira, Jorge R. Fernandes, Mário P. Véstias, and Horácio C. Neto DSD, page 74-81. IEEE Computer Society, (2009)
to dblp by dblp on Dec 28, 2009, 12:00 AM
URL | BibTeX
Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs.
Rui Duarte, Horácio C. Neto, and Mário Véstias DSD, page 273-280. IEEE Computer Society, (2009)
to dblp by dblp on Dec 28, 2009, 12:00 AM
URL | BibTeX
Decimal multiplier on FPGA using embedded binary multipliers.
Horácio C. Neto, and Mário P. Véstias FPL, page 197-202. IEEE, (2008)
to dblp by dblp on Feb 25, 2009, 12:00 AM
URL | BibTeX
Router Design for Application Specific Networks-on-Chip on Reconfigurable Systems.
Mário P. Véstias, and Horácio C. Neto FPL, page 389-394. IEEE, (2007)
to dblp by dblp on Nov 17, 2008, 12:00 AM
URL | BibTeX
Multiplier-based double precision floating point divider according to the IEEE-754 standard.
Vítor Silva, Rui Duarte, Mário P. Véstias, and Horácio C. Neto ARC, volume 4943 of Lecture Notes in Computer Science, page 260-265. Springer, (2008)
to dblp by dblp on Oct 21, 2008, 12:00 AM
URL | BibTeX
A Generic Network-on-Chip Architecture for Reconfigurable Systems: Implementation and Evaluation.
Mário P. Véstias, and Horácio C. Neto FPL, page 1-4. IEEE, (2006)
to dblp by dblp on Jul 19, 2007, 12:00 AM
URL | BibTeX
Area/Performance Improvement of NoC Architectures.
Mário P. Véstias, and Horácio C. Neto ARC, volume 3985 of Lecture Notes in Computer Science, page 193-198. Springer, (2006)
to dblp by dblp on Jun 28, 2007, 12:00 AM
URL | BibTeX
DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures.
Mário P. Véstias, and Horácio C. Neto SBCCI, page 85-. IEEE Computer Society, (2003)
to dblp by dblp on Jun 4, 2007, 12:00 AM
URL | BibTeX
Area and performance optimization of a generic network-on-chip architecture.
Mário P. Véstias, and Horácio C. Neto SBCCI, page 68-73. ACM, (2006)
to dblp by dblp on Dec 7, 2006, 12:00 AM
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Co-synthesis of a configurable SoC platform based on a network on chip architecture.
Mário P. Véstias, and Horácio C. Neto ASP-DAC, page 48-53. IEEE, (2006)
to dblp by dblp on Apr 28, 2006, 12:00 AM
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System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures.
Mário P. Véstias, and Horácio C. Neto IEEE International Workshop on Rapid System Prototyping, page 130-137. IEEE Computer Society, (2002)
to dblp by dblp on Jan 9, 2004, 12:00 AM
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