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(98)

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Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors.
Dan Nicolaescu, Alexander V. Veidenbaum, and Alexandru Nicolau DATE, page 11064-11069. IEEE Computer Society, (2003)
to dblp by dblp on Jan 6, 2012, 12:00 AM
URL | BibTeX
The Effect of Limited Network Bandwidth and its Utilization by Latency Hiding Techniques in Large-Scale Shared Memory Systems.
Sunil Kim, and Alexander V. Veidenbaum IEEE PACT, page 40-51. IEEE Computer Society, (1997)
to dblp by dblp on Jan 3, 2012, 12:00 AM
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Guest Editor's Introduction: Application-Specific Processors.
Alexander V. Veidenbaum IEEE Micro 24(3):8-9 (2004)
to dblp by dblp on Nov 3, 2011, 12:00 AM
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Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management.
Houman Homayoun, Avesta Sasan, Jean-Luc Gaudiot, and Alexander V. Veidenbaum IEEE Trans. VLSI Syst. 19(11):2081-2094 (2011)
to dblp by dblp on Nov 3, 2011, 12:00 AM
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MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits.
Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum, Hsin-Cheng Yao, Shahin Golshan, and Payam Heydari IEEE Trans. VLSI Syst. 19(12):2303-2316 (2011)
to dblp by dblp on Nov 3, 2011, 12:00 AM
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Interconnection network organization and its impact on performance and cost in shared memory multiprocessors.
Sunil Kim, and Alexander V. Veidenbaum Parallel Computing 25(3):283-309 (1999)
to dblp by dblp on Sep 14, 2011, 12:00 AM
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Pruning hardware evaluation space via correlation-driven application similarity analysis.
Rosario Cammarota, Arun Kejariwal, Paolo D'Alberto, Sapan Panigrahi, Alexander V. Veidenbaum, and Alexandru Nicolau Conf. Computing Frontiers, page 4. ACM, (2011)
to dblp by dblp on Aug 9, 2011, 12:00 AM
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A Data Cache with Dynamic Mapping.
Paolo D'Alberto, Alexandru Nicolau, and Alexander V. Veidenbaum LCPC, volume 2958 of Lecture Notes in Computer Science, page 436-450. Springer, (2003)
to dblp by dblp on Jul 6, 2011, 12:00 AM
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A Simple Low-Energy Instruction Wakeup Mechanism.
Marco A. Ramírez, Adrián Cristal, Alexander V. Veidenbaum, Luis Villa, and Mateo Valero ISHPC, volume 2858 of Lecture Notes in Computer Science, page 99-112. Springer, (2003)
to dblp by dblp on Jul 5, 2011, 12:00 AM
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Compiler-Directed Cache Line Size Adaptivity.
Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbaum, Alexandru Nicolau, and Rajesh K. Gupta Intelligent Memory Systems, volume 2107 of Lecture Notes in Computer Science, page 183-187. Springer, (2000)
to dblp by dblp on Jun 28, 2011, 12:00 AM
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Instruction Cache Prefetching Using Multilevel Branch Prediction.
Alexander V. Veidenbaum ISHPC, volume 1336 of Lecture Notes in Computer Science, page 51-70. Springer, (1997)
to dblp by dblp on Jun 16, 2011, 12:00 AM
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An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors.
Edward H. Gornish, and Alexander V. Veidenbaum International Journal of Parallel Programming 27(1):35-70 (1999)
to dblp by dblp on Jun 1, 2011, 12:00 AM
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Guest Editor's Introduction.
Alexander V. Veidenbaum International Journal of Parallel Programming 29(5):461-462 (2001)
to dblp by dblp on Jun 1, 2011, 12:00 AM
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Guest Editor's Introduction.
Alexander V. Veidenbaum International Journal of Parallel Programming 30(4):223-224 (2002)
to dblp by dblp on Jun 1, 2011, 12:00 AM
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Non-Sequential Instruction Cache Prefetching for Multiple-Issue Processors.
Alexander V. Veidenbaum, Qingbo Zhao, and Abduhl Shameer International Journal of High Speed Computing 10(1):115-140 (1999)
to dblp by dblp on Jan 31, 2011, 12:00 AM
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Efficient simulation of large-scale Spiking Neural Networks using CUDA graphics processors.
Jayram Moorkanikara Nageswaran, Nikil Dutt, Jeffrey L. Krichmar, Alex Nicolau, and Alexander V. Veidenbaum IJCNN, page 2145-2152. IEEE, (2009)
to dblp by dblp on Oct 4, 2010, 12:00 AM
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A centralized cache miss driven technique to improve processor power dissipation.
Houman Homayoun, Mohammad A. Makhzan, Jean-Luc Gaudiot, and Alexander V. Veidenbaum ICSAMOS, page 195-202. IEEE, (2008)
to dblp by dblp on Sep 7, 2010, 12:00 AM
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Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® CoreTM 2 Duo processor.
Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau, Xinmin Tian, Milind Girkar, Hideki Saito, and Utpal Banerjee ICSAMOS, page 132-141. IEEE, (2008)
to dblp by dblp on Sep 7, 2010, 12:00 AM
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Tight analysis of the performance potential of thread speculation using spec CPU 2006.
Arun Kejariwal, Xinmin Tian, Milind Girkar, Wei Li 0015, Sergey Kozhukhov, Utpal Banerjee, Alexandru Nicolau, Alexander V. Veidenbaum, and Constantine D. Polychronopoulos PPOPP, page 215-225. ACM, (2007)
to dblp by dblp on Sep 2, 2010, 12:00 AM
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On the performance potential of different types of speculative thread-level parallelism: The DL version of this paper includes corrections that were not made available in the printed proceedings.
Arun Kejariwal, Xinmin Tian, Wei Li 0015, Milind Girkar, Sergey Kozhukhov, Hideki Saito, Utpal Banerjee, Alexandru Nicolau, Alexander V. Veidenbaum, and Constantine D. Polychronopoulos ICS, page 24. ACM, (2006)
to dblp by dblp on Sep 2, 2010, 12:00 AM
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