BibSonomy :: author  :: Veredas ::

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publications

(16)

• Inhibitory unlearning: a mechanism for increasing the storage capacity in an attractor network.
  O. R. Manzano and Francisco J. Veredas and M. J. Guillen and Francisco J. Vico and J. Roman KES 177-180 (2000)
  to dblp by dblp on 2008-02-06 00:00:00
  | URL | BibTeX  
• Integrate-and-Fire Neural Networks with Monosynaptic-Like Correlated Activity.
  Hector Mesa and Francisco J. Veredas ICANN (1) 539-548 (2007)
  to dblp by dblp on 2007-09-17 00:00:00
  | URL | BibTeX  
• Self-organizing Maps of Spiking Neurons with Reduced Precision of Correlated Firing.
  Francisco J. Veredas and Luis A. Martínez and Hector Mesa ICANN (2) 349-358 (2007)
  to dblp by dblp on 2007-09-17 00:00:00
  | URL | BibTeX  
• LUT-based MPGAs for fast turnaround time conversion flow.
  Francisco-Javier Veredas and Michael Scheppler and Bumei Zhai and Hans-Jörg Pfleiderer ISCAS (2006)
  to dblp by dblp on 2007-07-23 00:00:00
  | URL | BibTeX  
• Automated Conversion From Lut-Based FPGAs to LUT-Based MPGAs.
  Francisco-Javier Veredas and Hans-Jörg Pfleiderer FPL 1-2 (2006)
  to dblp by dblp on 2007-07-19 00:00:00
  | URL | BibTeX  
• Evolving networks of integrate-and-fire neurons.
  Francisco J. Veredas and Francisco J. Vico and José M. Alonso Neurocomputing 69 1561-1569 (2006)
  to dblp by dblp on 2007-02-26 00:00:00
  | URL | BibTeX  
• Optimized synaptic conductance model for integrate-and-fire neurons.
  Francisco J. Veredas and Hector Mesa Artificial Intelligence and Soft Computing 98-103 (2006)
  to dblp by dblp on 2007-01-26 00:00:00
  | URL | BibTeX  
• Regular Routing Architecture for a LUT-based MPGA.
  Francisco-Javier Veredas and Michael Scheppler and Bumei Zhai and Hans-Jörg Pfleiderer ISVLSI 257-262 (2006)
  to dblp by dblp on 2007-01-08 00:00:00
  | URL | BibTeX  
• Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time.
  Francisco-Javier Veredas and Michael Scheppler and Hans-Jörg Pfleiderer DATE Designers' Forum 36-41 (2006)
  to dblp by dblp on 2006-09-15 00:00:00
  | URL | BibTeX  
• Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture.
  Bingfeng Mei and Francisco-Javier Veredas and Bart Masschelein FPL 622-625 (2005)
  to dblp by dblp on 2006-01-30 00:00:00
  | URL | BibTeX