Bibsonomy :: author  ::

bookmarks

publications

(27)

• Automated Design and Insertion of Optimal One-Hot Bus Encoders.
  Peter Wohl and John A. Waicukauski and Sanjay Patel VTS 409-415 (2007)
  to dblp by dblp on 2008-01-24 00:00:00
  | URL | BibTeX  
• Minimizing the Impact of Scan Compression.
  Peter Wohl and John A. Waicukauski and Rohit Kapur and S. Ramnath and Emil Gizdarski and Thomas W. Williams and P. Jaini VTS 67-74 (2007)
  to dblp by dblp on 2007-06-04 00:00:00
  | URL | BibTeX  
• On computing the sizes of detected delay faults.
  Vijay S. Iyengar and Barry K. Rosen and John A. Waicukauski IEEE Trans. on CAD of Integrated Circuits and Systems 9 299-312 (1990)
  to dblp by dblp on 2006-06-20 00:00:00
  | URL | BibTeX  
• Scalable selector architecture for x-tolerant deterministic BIST.
  Peter Wohl and John A. Waicukauski and Sanjay Patel DAC 934-939 (2004)
  to dblp by dblp on 2006-02-10 00:00:00
  | URL | BibTeX  
• Efficient compression and application of deterministic patterns in a logic BIST architecture.
  Peter Wohl and John A. Waicukauski and Sanjay Patel and Minesh B. Amin DAC 566-569 (2003)
  to dblp by dblp on 2006-02-10 00:00:00
  | URL | BibTeX  
• Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST.
  Peter Wohl and John A. Waicukauski and Sanjay Patel and Cy Hay and Emil Gizdarski and Ben Mathew VTS 359-365 (2005)
  to dblp by dblp on 2006-01-23 00:00:00
  | URL | BibTeX  
• Testing "untestable" faults in three-state circuits.
  Peter Wohl and John A. Waicukauski and Matthew Graf VTS 324-331 (1996)
  to dblp by dblp on 2004-07-16 00:00:00
  | URL | BibTeX  
• Using ATPG for clock rules checking in complex scan design.
  Peter Wohl and John A. Waicukauski VTS 130-136 (1997)
  to dblp by dblp on 2004-07-14 00:00:00
  | URL | BibTeX  
• X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture.
  Peter Wohl and John A. Waicukauski and Sanjay Patel and Minesh B. Amin ITC 727-736 (2003)
  to dblp by dblp on 2004-02-25 00:00:00
  | URL | BibTeX  
• Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique.
  Vishal Jain and John A. Waicukauski ITC 148-153 (2002)
  to dblp by dblp on 2004-01-14 00:00:00
  | URL | BibTeX