@inproceedings{conf/IEEEpact/WellsCS07,
	title = {Adapting to Intermittent Faults in Future Multicore Systems.},
	author = {Philip M. Wells and Koushik Chakraborty and Gurindar S. Sohi},
	booktitle = {PACT},
	crossref = {conf/IEEEpact/2007},
	pages = {431},
	publisher = {IEEE Computer Society},
	url = {http://dblp.uni-trier.de/db/conf/IEEEpact/IEEEpact2007.html#WellsCS07},
	year = {2007},
	biburl = {http://www.bibsonomy.org/bibtex/2c5e0fa113cc948fca4433ae1ce6d19c0/dblp},
	description = {dblp},
	ee = {http://doi.ieeecomputersociety.org/10.1109/PACT.2007.13}, date = {2008-08-20},
	keywords = {dblp }
}

@misc{wells_pact2007,
	title = {On Hiding Multicore Complexity from System Software},
	author = {Koushik Chakraborty Philip M. Wells and Gurindar S. Sohi},
	note = {Appears in Operating System support for Heterogeneous Multicore Architectures Workshop Program},
	year = {2007},
	biburl = {http://www.bibsonomy.org/bibtex/22311208bd32ba9f4abc1fb37dfd0e012/ykwok},
	abstract = {Future multicores will be very complex: at the very least,
they may contain statically heterogeneous cores, which are
designed with different engineering trade-offs, and dynami-
cally heterogeneouscores, which have different, and rapidly
changing, execution characteristics. Hardware companies
traditionally expose chips to system software at a very low
level, effectively saying, “Here is what we built, now do
something with it.”

However, there are several advantages to having the chip
itself manage these emerging complexities, while exposing a
more generic interface to software. We do not have all of the
answers for the appropriate role of system software, but we
do suggest that system architects should carefully consider
the benefits of abstraction when designing future systems.},
	keywords = {multicore os-scheduling }
}

@inproceedings{conf/asplos/WellsCS08,
	title = {Adapting to intermittent faults in multicore systems.},
	author = {Philip M. Wells and Koushik Chakraborty and Gurindar S. Sohi},
	booktitle = {ASPLOS},
	crossref = {conf/asplos/2008},
	editor = {Susan J. Eggers and James R. Larus},
	pages = {255-264},
	publisher = {ACM},
	url = {http://dblp.uni-trier.de/db/conf/asplos/asplos2008.html#WellsCS08},
	year = {2008},
	biburl = {http://www.bibsonomy.org/bibtex/2247d965631638509de5fcbd821e96a57/dblp},
	description = {dblp},
	date = {2008-04-08}, ee = {http://doi.acm.org/10.1145/1346281.1346314}, isbn = {978-1-59593-958-6},
	keywords = {dblp }
}

@inproceedings{sohi:multiscalar,
	title = {Multiscalar Processors},
	author = {Gurindar S. Sohi and Scott E. Breach and T. N. Vijaykumar},
	booktitle = {25 Years {ISCA}: Retrospectives and Reprints},
	pages = {521--532},
	url = {citeseer.nj.nec.com/sohi95multiscalar.html},
	year = {1998},
	biburl = {http://www.bibsonomy.org/bibtex/2e3dd8ffda4d93d3104022cc542440579/idsia},
	priority = {2}, citeulike-article-id = {2380350},
	keywords = {inaki }
}

@inproceedings{sohi:multiscalar,
	title = {Multiscalar Processors},
	author = {Gurindar S. Sohi and Scott E. Breach and T. N. Vijaykumar},
	booktitle = {25 Years {ISCA}: Retrospectives and Reprints},
	pages = {521--532},
	url = {citeseer.nj.nec.com/sohi95multiscalar.html},
	year = {1998},
	biburl = {http://www.bibsonomy.org/bibtex/2e3dd8ffda4d93d3104022cc542440579/schaul},
	description = {idsia},
	priority = {2}, citeulike-article-id = {2380350},
	keywords = {inaki }
}

@incollection{books/crc/tucker97/BurgerGS97,
	title = {Memory Systems.},
	author = {Doug Burger and James R. Goodman and Gurindar S. Sohi},
	booktitle = {The Computer Science and Engineering Handbook},
	crossref = {books/crc/tucker1997},
	editor = {Allen B. Tucker},
	pages = {447-461},
	publisher = {CRC Press},
	url = {http://dblp.uni-trier.de/db/books/collections/tucker97.html#BurgerGS97},
	year = {1997},
	biburl = {http://www.bibsonomy.org/bibtex/2b3eee4a0204c34388b69e2b9b841705c/dblp},
	description = {dblp},
	isbn = {0-8493-2909-4}, date = {2008-02-24},
	keywords = {dblp }
}

@inproceedings{Butts00,
	title = {A static power model for architects},
	address = {New York, NY, USA},
	author = {J. Adam Butts and Gurindar S. Sohi},
	booktitle = {MICRO 33: Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture},
	pages = {191--201},
	publisher = {ACM Press},
	year = {2000},
	biburl = {http://www.bibsonomy.org/bibtex/2e512f3f6653696fa8d897da780c092be/bernauer},
	description = {Euqation for estimation static power during design stage},
	abstract = {Static power dissipation due to transistor leakage constitutes an increasing fraction of the total power in modern semiconductor technologies. Current technology trends indicate that the contribution will increase rapidly, reaching one half of total power dissipation within three process generations. Developing power efficient products will require consideration of static power in the earliest phases of design, including architecture and microarchitecture definition. We propose a simple equation for estimating static power consumption at the architectural level: Pstatic=VCC·N·k design·Iˆleak, where VCC is the supply voltage, N is the number of transistors, kdesign is a design dependent parameter, and Iˆleak is a technology dependent parameter. This model enables high-level reasoning about the likely static power demands of alternative microarchitectures. Reasonably accurate values for the factors within the equation may be obtained directly from the high-level designs or by straightforward scaling arguments. The factors within the equation also suggest opportunities for static power optimization, including reducing the total number of devices, partitioning the design to allow for lower supply voltages or slower, less leaky transistors, turning off unused devices, favoring certain design styles, and favoring high bandwidth over low latency. Speculation is also examined as a means to employ slower transistors without a significant performance penalty},
	doi = {http://doi.acm.org/10.1145/360128.360148}, isbn = {1-58113-196-8}, location = {Monterey, California, United States},
	keywords = {design model power }
}

@inproceedings{conf/ics/ChangS07,
	title = {Cooperative cache partitioning for chip multiprocessors.},
	author = {Jichuan Chang and Gurindar S. Sohi},
	booktitle = {ICS},
	crossref = {conf/ics/2007},
	editor = {Burton J. Smith},
	pages = {242-252},
	publisher = {ACM},
	url = {http://dblp.uni-trier.de/db/conf/ics/ics2007.html#ChangS07},
	year = {2007},
	biburl = {http://www.bibsonomy.org/bibtex/2d99b966f908185ef9ed1ee235012c0e3/dblp},
	description = {dblp},
	ee = {http://doi.acm.org/10.1145/1274971.1275005}, isbn = {978-1-59593-768-1}, date = {2007-08-22},
	keywords = {dblp }
}

@inproceedings{conf/icdcn/SinghAS06,
	title = {A Signalling Technique for Disseminating Neighbouring AP Channel Information to Mobile Stations.},
	author = {Gurpal Singh and Ajay Pal Singh Atwal and B. S. Sohi},
	booktitle = {ICDCN},
	crossref = {conf/icdcn/2006},
	editor = {Soma Chaudhuri and Samir R. Das and Himadri S. Paul and Srikanta Tirthapura},
	pages = {594-599},
	publisher = {Springer},
	series = {Lecture Notes in Computer Science},
	url = {http://dblp.uni-trier.de/db/conf/icdcn/icdcn2006.html#SinghAS06},
	volume = {4308},
	year = {2006},
	biburl = {http://www.bibsonomy.org/bibtex/2350362436ccdc7e2affbe7c4cb0f3ba9/dblp},
	description = {dblp},
	ee = {http://dx.doi.org/10.1007/11947950_64}, isbn = {3-540-68139-6}, date = {2007-05-21},
	keywords = {dblp }
}

@inproceedings{conf/asplos/ChakrabortyWS06,
	title = {Computation spreading: employing hardware migration to specialize CMP cores on-the-fly.},
	author = {Koushik Chakraborty and Philip M. Wells and Gurindar S. Sohi},
	booktitle = {ASPLOS},
	crossref = {conf/asplos/2006},
	editor = {John Paul Shen and Margaret Martonosi},
	pages = {283-292},
	publisher = {ACM},
	url = {http://dblp.uni-trier.de/db/conf/asplos/asplos2006.html#ChakrabortyWS06},
	year = {2006},
	biburl = {http://www.bibsonomy.org/bibtex/207c97662d0ac58a4478bdca71ee1d382/dblp},
	description = {dblp},
	ee = {http://doi.acm.org/10.1145/1168857.1168893}, isbn = {1-59593-451-0}, date = {2007-05-15},
	keywords = {dblp }
}