@inproceedings{Vogel2006Timeinterleaved,
	title = {Time-interleaved analog-to-digital converters: status and future directions},
	author = {C. Vogel and H. Johansson},
	booktitle = {Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on},
	journal = {Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on},
	pages = {4 pp.+},
	url = {http://dx.doi.org/10.1109/ISCAS.2006.1693352},
	year = {2006},
	biburl = {http://www.bibsonomy.org/bibtex/269437a8a7364c53923c6f548f9b16b5f/peteru},
	abstract = {We discuss time-interleaved analog-to-digital converters (ADCs) as a prime example of merging analog and digital signal processing. A time-interleaved ADC (TI-ADC) consists of M parallel channel ADCs that alternately take samples from the input signal, where the sampling rate can be increased by the number of channels compared to a single channel. We recall the advantages of time interleaving and investigate the problems involved. In particular, we explain the error behavior of mismatches among the channels, which distort the output signal and reduce the system performance significantly, and provide a concise framework for dealing with them. Based on this analysis, we review the principle possibilities of calibrating TI-ADCs, where we point out the necessities and advantages of digital enhancement. To this end, we discuss open issues of channel mismatch identification as well as channel mismatch correction.},
	posted-at = {2008-07-14 21:06:00}, citeulike-article-id = {3000175}, priority = {5}, doi = {10.1109/ISCAS.2006.1693352},
	keywords = {ad, adc, analog-to-digital, analysis, compensation, converter, correction, error, gain, identification, methods, mismatches, modeling, offset, parallel, principles, status, time-interleaved }
}