@inproceedings{1152162,
	title = {Core architecture optimization for heterogeneous chip multiprocessors},
	address = {New York, NY, USA},
	author = {Rakesh Kumar and Dean M. Tullsen and Norman P. Jouppi},
	booktitle = {PACT '06: Proceedings of the 15th international conference on Parallel architectures and compilation techniques},
	pages = {23--32},
	publisher = {ACM},
	url = {http://portal.acm.org/citation.cfm?id=1152154.1152162&coll=&dl=#},
	year = {2006},
	biburl = {http://www.bibsonomy.org/bibtex/2eec02d0202e6e7ba333d3530261da68d/ykwok},
	description = {Core architecture optimization for heterogeneous chip multiprocessors},
	abstract = {Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to design such a processor; instead, they started with an assumed combination of pre-existing cores.This work assumes the flexibility to design a multi-core architecture from the ground up and seeks to address the following question: what should be the characteristics of the cores for a heterogeneous multi processor for the highest area or power efficiency? The study is done for varying degrees of thread-level parallelism and for different area and power budgets.The most efficient chip multiprocessors are shown to be heterogeneous, with each core customized to a different subset of application characteristics - no single core is necessarily well suited to all applications. The performance ordering of cores on such processors is different for different applications; there is only a partial ordering among cores in terms of resources and complexity. This methodology produces performance gains as high as 40%. The performance improvements come with the added cost of customization.},
	location = {Seattle, Washington, USA}, isbn = {1-59593-264-X}, doi = {http://doi.acm.org/10.1145/1152154.1152162},
	keywords = {heterogeneous multicore }
}