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%0 Journal Article
%1 journals/jbcs/MeloSSLMM15
%A Melo, Lucas T.
%A Santana, S. H. C.
%A Silva-Filho, Abel G.
%A de Lima, Manoel Eusébio
%A de Medeiros, Victor Wanderley Costa
%A Marinho, Marcelo L. M.
%D 2015
%J J. Braz. Comput. Soc.
%K dblp
%N 1
%P 12:1-12:11
%T An inter-FPGA communication bus with error detection and dynamic clock phase adjustment.
%U http://dblp.uni-trier.de/db/journals/jbcs/jbcs21.html#MeloSSLMM15
%V 21
@article{journals/jbcs/MeloSSLMM15,
added-at = {2024-03-04T00:00:00.000+0100},
author = {Melo, Lucas T. and Santana, S. H. C. and Silva-Filho, Abel G. and de Lima, Manoel Eusébio and de Medeiros, Victor Wanderley Costa and Marinho, Marcelo L. M.},
biburl = {https://www.bibsonomy.org/bibtex/2e2a1d03d77e0f9d9d88bbc3d34c912e5/dblp},
ee = {https://www.wikidata.org/entity/Q59430719},
interhash = {0515eeb319a63367dea837a798388385},
intrahash = {e2a1d03d77e0f9d9d88bbc3d34c912e5},
journal = {J. Braz. Comput. Soc.},
keywords = {dblp},
number = 1,
pages = {12:1-12:11},
timestamp = {2024-04-08T09:41:43.000+0200},
title = {An inter-FPGA communication bus with error detection and dynamic clock phase adjustment.},
url = {http://dblp.uni-trier.de/db/journals/jbcs/jbcs21.html#MeloSSLMM15},
volume = 21,
year = 2015
}