%0 Conference Paper %1 conf/vlsid/RoyIN00 %A Roy, Subir K. %A Iwashita, Hiroaki %A Nakata, Tsuneo %B VLSI Design %D 2000 %I IEEE Computer Society %K dblp %P 418-423 %T Dataflow Analysis for Resource Contention and Register Leakage Properties. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2000.html#RoyIN00 %@ 0-7695-0487-6

@inproceedings{conf/vlsid/RoyIN00, added-at = {2023-03-24T00:00:00.000+0100}, author = {Roy, Subir K. and Iwashita, Hiroaki and Nakata, Tsuneo}, biburl = {https://www.bibsonomy.org/bibtex/22870dabbfdc87d4c4e5a71ed3434bfd6/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2000}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2000.812643}, interhash = {0c566451ab1560108ef1bcbaafe8ed81}, intrahash = {2870dabbfdc87d4c4e5a71ed3434bfd6}, isbn = {0-7695-0487-6}, keywords = {dblp}, pages = {418-423}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:19:01.000+0200}, title = {Dataflow Analysis for Resource Contention and Register Leakage Properties.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2000.html#RoyIN00}, year = 2000 }