%0 Conference Paper %1 conf/vlsid/RajaAB05 %A Raja, Tezaswi %A Agrawal, Vishwani D. %A Bushnell, Michael L. %B VLSI Design %D 2005 %I IEEE Computer Society %K dblp %P 598-605 %T Variable Input Delay CMOS Logic for Low Power Design. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2005.html#RajaAB05 %@ 0-7695-2264-5

@inproceedings{conf/vlsid/RajaAB05, added-at = {2023-03-24T00:00:00.000+0100}, author = {Raja, Tezaswi and Agrawal, Vishwani D. and Bushnell, Michael L.}, biburl = {https://www.bibsonomy.org/bibtex/2f470396beb7f8cd0dc8bac710cee4b8e/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2005}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2005.167}, interhash = {077c306c8786ed221f2ea8441adabb99}, intrahash = {f470396beb7f8cd0dc8bac710cee4b8e}, isbn = {0-7695-2264-5}, keywords = {dblp}, pages = {598-605}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:18:41.000+0200}, title = {Variable Input Delay CMOS Logic for Low Power Design.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2005.html#RajaAB05}, year = 2005 }