%0 Conference Paper %1 conf/pdcat/LiuSKK04 %A Liu, Zhe %A Shim, JeoungChill %A Kurino, Hiroyuki %A Koyanagi, Mitsumasa %B PDCAT %D 2004 %E Liew, Kim-Meow %E Shen, Hong %E See, Simon %E Cai, Wentong %E Fan, Pingzhi %E Horiguchi, Susumu %I Springer %K dblp %P 564-569 %T Design and Evaluation of a Novel Real-Shared Cache Module for High Performance Parallel Processor Chip. %U http://dblp.uni-trier.de/db/conf/pdcat/pdcat2004.html#LiuSKK04 %V 3320 %@ 3-540-24013-6

@inproceedings{conf/pdcat/LiuSKK04, added-at = {2017-05-22T00:00:00.000+0200}, author = {Liu, Zhe and Shim, JeoungChill and Kurino, Hiroyuki and Koyanagi, Mitsumasa}, biburl = {https://www.bibsonomy.org/bibtex/2b0cd86aaa39f5aa784394ce58da017ca/dblp}, booktitle = {PDCAT}, crossref = {conf/pdcat/2004}, editor = {Liew, Kim-Meow and Shen, Hong and See, Simon and Cai, Wentong and Fan, Pingzhi and Horiguchi, Susumu}, ee = {https://doi.org/10.1007/978-3-540-30501-9_108}, interhash = {1ccd35a1f4fafe17928b112e6328db3f}, intrahash = {b0cd86aaa39f5aa784394ce58da017ca}, isbn = {3-540-24013-6}, keywords = {dblp}, pages = {564-569}, publisher = {Springer}, series = {Lecture Notes in Computer Science}, timestamp = {2020-06-13T11:41:45.000+0200}, title = {Design and Evaluation of a Novel Real-Shared Cache Module for High Performance Parallel Processor Chip.}, url = {http://dblp.uni-trier.de/db/conf/pdcat/pdcat2004.html#LiuSKK04}, volume = 3320, year = 2004 }