%0 Conference Paper %1 conf/aspdac/AgarwalW06 %A Agarwal, Vineet %A Wang, Janet Meiling %B ASP-DAC %D 2006 %E Hirose, Fumiyasu %I IEEE %K dblp %P 718-723 %T Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA). %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2006.html#AgarwalW06 %@ 0-7803-9451-8

@inproceedings{conf/aspdac/AgarwalW06, added-at = {2018-11-06T00:00:00.000+0100}, author = {Agarwal, Vineet and Wang, Janet Meiling}, biburl = {https://www.bibsonomy.org/bibtex/27951ff22afbd51c6fc1ca89d552f0121/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2006}, editor = {Hirose, Fumiyasu}, ee = {https://doi.org/10.1145/1118299.1118467}, interhash = {20639b23fa0275d0ade17981db5ff8fe}, intrahash = {7951ff22afbd51c6fc1ca89d552f0121}, isbn = {0-7803-9451-8}, keywords = {dblp}, pages = {718-723}, publisher = {IEEE}, timestamp = {2019-10-17T16:45:43.000+0200}, title = {Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA).}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2006.html#AgarwalW06}, year = 2006 }