%0 Conference Paper %1 7346275 %A Meinl, F. %A Schubert, E. %A Kunert, M. %A Blume, H. %B Radar Conference (EuRAD), 2015 European %D 2015 %K 2015 MIMO fpga myown %P 213-216 %R 10.1109/EuRAD.2015.7346275 %T Realtime FPGA-based processing unit for a high-resolution automotive MIMO radar platform %U http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7346275 %X Next generations of high-resolution automotive radar sensors rely on powerful, real-time capable processing units. High sampling rates, large antenna arrays as well as hard real-time constraints require the use of both parallel architectures and high-bandwidth memory interfaces. This paper presents a novel architecture of a FPGA-based multiple-input multiple-output (MIMO) radar sensor processing unit. Sampling rates up to 250 MSPS and a maximum of 16 parallel receiving channels can be used, resulting in a maximum data rate of 56GBit/s. The processing chain consists of a flexible FIR filter, a range-Doppler processing unit using windowed FFTs and an ordered statistics constant-false-alarm-rate (OS-CFAR) unit for optimal target detection and data reduction. The realized target system is composed of a Virtex7-FPGA and a 1GByte SDRAM memory. The resource usage of the FPGA implementation is analyzed in order to provide estimations for future system designs. Finally, the resulting performance of the system is verified in connection with a prototype MIMO radar front-end. High-resolution measurements of moving scenes have been carried out to validate the correct operation of the system.

@inproceedings{7346275, abstract = {Next generations of high-resolution automotive radar sensors rely on powerful, real-time capable processing units. High sampling rates, large antenna arrays as well as hard real-time constraints require the use of both parallel architectures and high-bandwidth memory interfaces. This paper presents a novel architecture of a FPGA-based multiple-input multiple-output (MIMO) radar sensor processing unit. Sampling rates up to 250 MSPS and a maximum of 16 parallel receiving channels can be used, resulting in a maximum data rate of 56GBit/s. The processing chain consists of a flexible FIR filter, a range-Doppler processing unit using windowed FFTs and an ordered statistics constant-false-alarm-rate (OS-CFAR) unit for optimal target detection and data reduction. The realized target system is composed of a Virtex7-FPGA and a 1GByte SDRAM memory. The resource usage of the FPGA implementation is analyzed in order to provide estimations for future system designs. Finally, the resulting performance of the system is verified in connection with a prototype MIMO radar front-end. High-resolution measurements of moving scenes have been carried out to validate the correct operation of the system.}, added-at = {2016-04-20T13:06:18.000+0200}, author = {Meinl, F. and Schubert, E. and Kunert, M. and Blume, H.}, biburl = {https://www.bibsonomy.org/bibtex/2cc82027015390cc0bf2adb19fe95c36b/imsl3s}, booktitle = {Radar Conference (EuRAD), 2015 European}, description = {IEEE Xplore Abstract - Realtime FPGA-based processing unit for a high-resolution automotive MIMO radar platform}, doi = {10.1109/EuRAD.2015.7346275}, interhash = {2c282659038482f219b4282242890334}, intrahash = {cc82027015390cc0bf2adb19fe95c36b}, keywords = {2015 MIMO fpga myown}, month = {Sept}, pages = {213-216}, timestamp = {2016-04-20T13:06:18.000+0200}, title = {Realtime FPGA-based processing unit for a high-resolution automotive MIMO radar platform}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7346275}, year = 2015 }