%0 Conference Paper %1 conf/vlsi-dat/HoCCL12 %A Ho, Kevin %A Chou, Tsung-Yi %A Chen, Po-Kai %A Liou, David J. %B VLSI-DAT %D 2012 %I IEEE %K dblp %P 1-5 %T High speed DDR2/3 PHY and dual CPU core design for 28nm SoC. %U http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2012.html#HoCCL12 %@ 978-1-4577-2080-2

@inproceedings{conf/vlsi-dat/HoCCL12, added-at = {2015-09-29T00:00:00.000+0200}, author = {Ho, Kevin and Chou, Tsung-Yi and Chen, Po-Kai and Liou, David J.}, biburl = {https://www.bibsonomy.org/bibtex/23e68379f6d22d45d3c50e790bb8bd7c2/dblp}, booktitle = {VLSI-DAT}, crossref = {conf/vlsi-dat/2012}, ee = {http://dx.doi.org/10.1109/VLSI-DAT.2012.6212637}, interhash = {6482e0a70be190acd8a2ed6cc6cd9e90}, intrahash = {3e68379f6d22d45d3c50e790bb8bd7c2}, isbn = {978-1-4577-2080-2}, keywords = {dblp}, pages = {1-5}, publisher = {IEEE}, timestamp = {2015-09-30T11:34:11.000+0200}, title = {High speed DDR2/3 PHY and dual CPU core design for 28nm SoC.}, url = {http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2012.html#HoCCL12}, year = 2012 }