%0 Conference Paper %1 conf/vlsid/SenGuptaIL12 %A SenGupta, Breeta %A Ingelsson, Urban %A Larsson, Erik %B VLSI Design %D 2012 %E Agrawal, Vishwani D. %E Chakradhar, Srimat T. %I IEEE Computer Society %K dblp %P 442-447 %T Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2012.html#SenGuptaIL12 %@ 978-1-4673-0438-2

@inproceedings{conf/vlsid/SenGuptaIL12, added-at = {2023-03-24T00:00:00.000+0100}, author = {SenGupta, Breeta and Ingelsson, Urban and Larsson, Erik}, biburl = {https://www.bibsonomy.org/bibtex/2f2a3a0b3c672b514dbae371e895a269a/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2012}, editor = {Agrawal, Vishwani D. and Chakradhar, Srimat T.}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2012.111}, interhash = {68c7f049b2b20a628c2151f15f22c406}, intrahash = {f2a3a0b3c672b514dbae371e895a269a}, isbn = {978-1-4673-0438-2}, keywords = {dblp}, pages = {442-447}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T01:05:21.000+0200}, title = {Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2012.html#SenGuptaIL12}, year = 2012 }