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%0 Conference Paper
%1 conf/vlsid/SinhaZFWRVS16
%A Sinha, Debjit
%A Zolotov, Vladimir
%A Fluhr, Eric
%A Wood, Michael H.
%A Ritzinger, Jeffrey
%A Venkateswaran, Natesan
%A Shuma, Stephen
%B VLSI Design
%D 2016
%I IEEE Computer Society
%K dblp
%P 493-498
%T Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains.
%U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2016.html#SinhaZFWRVS16
%@ 978-1-4673-8700-2
@inproceedings{conf/vlsid/SinhaZFWRVS16,
added-at = {2016-05-27T00:00:00.000+0200},
author = {Sinha, Debjit and Zolotov, Vladimir and Fluhr, Eric and Wood, Michael H. and Ritzinger, Jeffrey and Venkateswaran, Natesan and Shuma, Stephen},
biburl = {https://www.bibsonomy.org/bibtex/2b660097b5f5addc8845504c05aa165c0/dblp},
booktitle = {VLSI Design},
crossref = {conf/vlsid/2016},
ee = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2016.17},
interhash = {6c512c654fec47be547e538364e983ef},
intrahash = {b660097b5f5addc8845504c05aa165c0},
isbn = {978-1-4673-8700-2},
keywords = {dblp},
pages = {493-498},
publisher = {IEEE Computer Society},
timestamp = {2016-05-28T11:58:59.000+0200},
title = {Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains.},
url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2016.html#SinhaZFWRVS16},
year = 2016
}