Conference,
Fault Modeling for Verilog Register Transfer Level
(2013)
Abstract
As the complexity of Very Large Scale Integration
(VLSI) increases, testing becomes tedious. Currently fault
models are used to test digital circuits at gate level or at levels
lower than gate. Modeling faults at these levels, leads to
increase in the design cycle time period. Hence, there is a
need to explore new approaches for modeling faults at higher
levels. This paper proposes fault modeling at the Register
Transfer Level (RTL) for digital circuits. Using this level of
modeling, results are obtained for fault coverage, area and
test patterns. A software prototype, FEVER, has been developed
in C which reads a RTL description and generates two output
files: one a modified RTL with test features and two a file
consisting of set of test patterns. These modified RTL and test
patterns are further used for fault simulation and fault
coverage analysis. Comparison is performed between the RTL
and Gate level modeling for ISCAS benchmarks and the
results of the same are presented. Results are obtained using
Synopsys, TetraMax and it is shown that it is possible to achieve
100% fault coverage with no area overhead at the RTL level.
