Article,
Area and Power Modeling for Networks-on-Chip with Layout Awareness.
P. Meloni, I. Loi, F. Angiolini, S. Carta, M. Barbaro, L. Raffo, and L. Benini.VLSI Design, (2007)
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- article
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- 2007
- journal
- VLSI Design
- pages
- 50285:1-50285:12
- volume
- 2007
- ee
- https://doi.org/10.1155/2007/50285
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- http://dblp.uni-trier.de/db/journals/vlsi/vlsi2007.html#MeloniLACBRB07
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- please select -%0 Journal Article
%1 journals/vlsi/MeloniLACBRB07
%A Meloni, Paolo
%A Loi, Igor
%A Angiolini, Federico
%A Carta, Salvatore
%A Barbaro, Massimo
%A Raffo, Luigi
%A Benini, Luca
%D 2007
%J VLSI Design
%K dblp
%P 50285:1-50285:12
%T Area and Power Modeling for Networks-on-Chip with Layout Awareness.
%U http://dblp.uni-trier.de/db/journals/vlsi/vlsi2007.html#MeloniLACBRB07
%V 2007
@article{journals/vlsi/MeloniLACBRB07,
added-at = {2018-08-16T00:00:00.000+0200},
author = {Meloni, Paolo and Loi, Igor and Angiolini, Federico and Carta, Salvatore and Barbaro, Massimo and Raffo, Luigi and Benini, Luca},
biburl = {https://www.bibsonomy.org/bibtex/2093f58c89165bf4675fa37e335709424/dblp},
ee = {https://doi.org/10.1155/2007/50285},
interhash = {8442b76bf51892612419eb44d38c3010},
intrahash = {093f58c89165bf4675fa37e335709424},
journal = {VLSI Design},
keywords = {dblp},
pages = {50285:1-50285:12},
timestamp = {2018-08-17T11:38:54.000+0200},
title = {Area and Power Modeling for Networks-on-Chip with Layout Awareness.},
url = {http://dblp.uni-trier.de/db/journals/vlsi/vlsi2007.html#MeloniLACBRB07},
volume = 2007,
year = 2007
}