%0 Conference Paper %1 conf/ismvl/ParkYYK04 %A Park, Soo Jin %A Yoon, Byoung Hee %A Yoon, Kwang Sub %A Kim, Heung Soo %B ISMVL %D 2004 %I IEEE Computer Society %K dblp %P 198-203 %T Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. %U http://dblp.uni-trier.de/db/conf/ismvl/ismvl2004.html#ParkYYK04 %@ 0-7695-2130-4

@inproceedings{conf/ismvl/ParkYYK04, added-at = {2023-03-23T00:00:00.000+0100}, author = {Park, Soo Jin and Yoon, Byoung Hee and Yoon, Kwang Sub and Kim, Heung Soo}, biburl = {https://www.bibsonomy.org/bibtex/2c301b192ef6b3bfbdc54ab6d626e79e6/dblp}, booktitle = {ISMVL}, crossref = {conf/ismvl/2004}, ee = {https://doi.ieeecomputersociety.org/10.1109/ISMVL.2004.1319941}, interhash = {8aaab458e4381579c9cc6b8c44fbd488}, intrahash = {c301b192ef6b3bfbdc54ab6d626e79e6}, isbn = {0-7695-2130-4}, keywords = {dblp}, pages = {198-203}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T17:17:45.000+0200}, title = {Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit.}, url = {http://dblp.uni-trier.de/db/conf/ismvl/ismvl2004.html#ParkYYK04}, year = 2004 }