%0 Conference Paper %1 conf/ats/HsuHCWHWL02 %A Hsu, Huan-Shan %A Huang, Jing-Reng %A Cheng, Kuo-Liang %A Wang, Chih-Wea %A Huang, Chih-Tsun %A Wu, Cheng-Wen %A Lin, Youn-Long %B Asian Test Symposium %D 2002 %I IEEE Computer Society %K dblp %P 411- %T Test Scheduling and Test Access Architecture Optimization for System-on-Chip. %U http://dblp.uni-trier.de/db/conf/ats/ats2002.html#HsuHCWHWL02 %@ 0-7695-1825-7

@inproceedings{conf/ats/HsuHCWHWL02, added-at = {2023-09-30T00:00:00.000+0200}, author = {Hsu, Huan-Shan and Huang, Jing-Reng and Cheng, Kuo-Liang and Wang, Chih-Wea and Huang, Chih-Tsun and Wu, Cheng-Wen and Lin, Youn-Long}, biburl = {https://www.bibsonomy.org/bibtex/2d621704d81a9a27cc7b5c5aeb9a0d163/dblp}, booktitle = {Asian Test Symposium}, crossref = {conf/ats/2002}, ee = {https://doi.ieeecomputersociety.org/10.1109/ATS.2002.1181746}, interhash = {8c96c0db022745c9f8758c2667e3c1cc}, intrahash = {d621704d81a9a27cc7b5c5aeb9a0d163}, isbn = {0-7695-1825-7}, keywords = {dblp}, pages = {411-}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T06:35:29.000+0200}, title = {Test Scheduling and Test Access Architecture Optimization for System-on-Chip.}, url = {http://dblp.uni-trier.de/db/conf/ats/ats2002.html#HsuHCWHWL02}, year = 2002 }