%0 Conference Paper %1 conf/vdat/GargD16 %A Garg, Sasha %A Darak, Sumit Jagdish %B VDAT %D 2016 %I IEEE %K dblp %P 1-5 %T FPGA implementation of high speed reconfigurable filter bank for multi-standard wireless communication receivers. %U http://dblp.uni-trier.de/db/conf/vdat/vdat2016.html#GargD16 %@ 978-1-5090-1422-4

@inproceedings{conf/vdat/GargD16, added-at = {2019-09-25T00:00:00.000+0200}, author = {Garg, Sasha and Darak, Sumit Jagdish}, biburl = {https://www.bibsonomy.org/bibtex/2bf3bf66be422058d31a99b5adec6802f/dblp}, booktitle = {VDAT}, crossref = {conf/vdat/2016}, ee = {https://doi.org/10.1109/ISVDAT.2016.8064855}, interhash = {91c0b4301b2a7e498b4253c69606d8a7}, intrahash = {bf3bf66be422058d31a99b5adec6802f}, isbn = {978-1-5090-1422-4}, keywords = {dblp}, pages = {1-5}, publisher = {IEEE}, timestamp = {2019-09-26T12:51:47.000+0200}, title = {FPGA implementation of high speed reconfigurable filter bank for multi-standard wireless communication receivers.}, url = {http://dblp.uni-trier.de/db/conf/vdat/vdat2016.html#GargD16}, year = 2016 }