%0 Conference Paper %1 conf/vlsid/DaveAB05 %A Dave, Kunal K. %A Agrawal, Vishwani D. %A Bushnell, Michael L. %B VLSI Design %D 2005 %I IEEE Computer Society %K dblp %P 723-729 %T Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2005.html#DaveAB05 %@ 0-7695-2264-5

@inproceedings{conf/vlsid/DaveAB05, added-at = {2023-03-24T00:00:00.000+0100}, author = {Dave, Kunal K. and Agrawal, Vishwani D. and Bushnell, Michael L.}, biburl = {https://www.bibsonomy.org/bibtex/26797dfa5382016cc87d20bacc7fd78c5/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2005}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2005.166}, interhash = {9a620dbf6c1bd0c1ded1ccff1ae0ecde}, intrahash = {6797dfa5382016cc87d20bacc7fd78c5}, isbn = {0-7695-2264-5}, keywords = {dblp}, pages = {723-729}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:18:41.000+0200}, title = {Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2005.html#DaveAB05}, year = 2005 }