%0 Journal Article %1 journals/jssc/HsiehCLC16 %A Hsieh, Min-Han %A Chen, Liang-Hsin %A Liu, Shen-Iuan %A Chen, Charlie Chung-Ping %D 2016 %J IEEE J. Solid State Circuits %K dblp %N 2 %P 412-427 %T A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS. %U http://dblp.uni-trier.de/db/journals/jssc/jssc51.html#HsiehCLC16 %V 51

@article{journals/jssc/HsiehCLC16, added-at = {2020-08-30T00:00:00.000+0200}, author = {Hsieh, Min-Han and Chen, Liang-Hsin and Liu, Shen-Iuan and Chen, Charlie Chung-Ping}, biburl = {https://www.bibsonomy.org/bibtex/2559c75e8632cd7c73345f3c255038ce0/dblp}, ee = {https://doi.org/10.1109/JSSC.2015.2494603}, interhash = {9e03415e930ac10436ca6ab8389e8112}, intrahash = {559c75e8632cd7c73345f3c255038ce0}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 2, pages = {412-427}, timestamp = {2020-08-31T11:40:31.000+0200}, title = {A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc51.html#HsiehCLC16}, volume = 51, year = 2016 }