%0 Conference Paper %1 conf/date/LiuCHWCDN14 %A Liu, Chian-Wei %A Chiang, Chang-En %A Huang, Ching-Yi %A Wang, Chun-Yao %A Chen, Yung-Chih %A Datta, Suman %A Narayanan, Vijaykrishnan %B DATE %D 2014 %E Fettweis, Gerhard P. %E Nebel, Wolfgang %I European Design and Automation Association %K dblp %P 1-4 %T Width minimization in the Single-Electron Transistor array synthesis. %U http://dblp.uni-trier.de/db/conf/date/date2014.html#LiuCHWCDN14 %@ 978-3-9815370-2-4

@inproceedings{conf/date/LiuCHWCDN14, added-at = {2017-05-23T00:00:00.000+0200}, author = {Liu, Chian-Wei and Chiang, Chang-En and Huang, Ching-Yi and Wang, Chun-Yao and Chen, Yung-Chih and Datta, Suman and Narayanan, Vijaykrishnan}, biburl = {https://www.bibsonomy.org/bibtex/2e45ba5ad3acda6d6f31af6a662c7bbab/dblp}, booktitle = {DATE}, crossref = {conf/date/2014}, editor = {Fettweis, Gerhard P. and Nebel, Wolfgang}, ee = {http://dl.acm.org/citation.cfm?id=2616755}, interhash = {a46344f2e0ef611a02adf229c99ebe46}, intrahash = {e45ba5ad3acda6d6f31af6a662c7bbab}, isbn = {978-3-9815370-2-4}, keywords = {dblp}, pages = {1-4}, publisher = {European Design and Automation Association}, timestamp = {2017-12-07T22:59:13.000+0100}, title = {Width minimization in the Single-Electron Transistor array synthesis.}, url = {http://dblp.uni-trier.de/db/conf/date/date2014.html#LiuCHWCDN14}, year = 2014 }