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%0 Conference Paper
%1 conf/itc/RaviJ01
%A Ravi, Srivaths
%A Jha, Niraj K.
%B ITC
%D 2001
%I IEEE Computer Society
%K dblp
%P 1068-1077
%T Fast test generation for circuits with RTL and gate-level views.
%U http://dblp.uni-trier.de/db/conf/itc/itc2001.html#RaviJ01
%@ 0-7803-7169-0
@inproceedings{conf/itc/RaviJ01,
added-at = {2023-03-23T00:00:00.000+0100},
author = {Ravi, Srivaths and Jha, Niraj K.},
biburl = {https://www.bibsonomy.org/bibtex/2f45ee55c75979e880004be3318ea8534/dblp},
booktitle = {ITC},
crossref = {conf/itc/2001},
ee = {https://doi.ieeecomputersociety.org/10.1109/TEST.2001.966733},
interhash = {ad11e3d5635da046589c79eec96eb9c1},
intrahash = {f45ee55c75979e880004be3318ea8534},
isbn = {0-7803-7169-0},
keywords = {dblp},
pages = {1068-1077},
publisher = {IEEE Computer Society},
timestamp = {2024-04-10T04:28:56.000+0200},
title = {Fast test generation for circuits with RTL and gate-level views.},
url = {http://dblp.uni-trier.de/db/conf/itc/itc2001.html#RaviJ01},
year = 2001
}