%0 Conference Paper %1 conf/date/KangPLBM16 %A Kang, Kyungsu %A Park, Sangho %A Lee, Jong-Bae %A Benini, Luca %A Micheli, Giovanni De %B DATE %D 2016 %E Fanucci, Luca %E Teich, Jürgen %I IEEE %K dblp %P 1465-1468 %T A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache. %U http://dblp.uni-trier.de/db/conf/date/date2016.html#KangPLBM16 %@ 978-3-9815-3707-9

@inproceedings{conf/date/KangPLBM16, added-at = {2021-08-09T00:00:00.000+0200}, author = {Kang, Kyungsu and Park, Sangho and Lee, Jong-Bae and Benini, Luca and Micheli, Giovanni De}, biburl = {https://www.bibsonomy.org/bibtex/26edd8b8de02acfad01583cb8895623ca/dblp}, booktitle = {DATE}, crossref = {conf/date/2016}, editor = {Fanucci, Luca and Teich, Jürgen}, ee = {https://ieeexplore.ieee.org/document/7459541/}, interhash = {b05b8fd6bf5a31317a2d08fa652c3db5}, intrahash = {6edd8b8de02acfad01583cb8895623ca}, isbn = {978-3-9815-3707-9}, keywords = {dblp}, pages = {1465-1468}, publisher = {IEEE}, timestamp = {2024-04-10T06:47:58.000+0200}, title = {A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache.}, url = {http://dblp.uni-trier.de/db/conf/date/date2016.html#KangPLBM16}, year = 2016 }